82375EB datasheet(34/131 Pages) INTEL

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82375EBSB

Bit

Description

Auto-PEREQ

Control (APC)

APC EnablesDisables control of the auto-PEREQ

function when

GAT mode is enabled via bit 0 (GATe1) When APCe1 (and GATe1) the PEREQ

signal is

asserted whenever the EISAHLDA signal is asserted When APCe0 the PEREQ

signal is not

automatically asserted but it will be activated upon PCI Bus request from any PCI agent After

PCIRST

APCe1 (enabled) See note

Reserved

Master Retry Timer (MRT)

This 2-bit field determines the number of PCICLKs after the first retry that

a PCI initiator’s bus request will be masked Note that for proper system operation this register must

be programmed with either 01 10 11

Bits 43

Operation

Timer disabled Retries never masked (Default)

Retries unmasked after 16 PCICLK’s

Retries unmasked after 32 PCICLK’s

Retries unmasked after 64 PCICLK’s

Bus Park (BP)

When BPe1 the PCEB will park CPUREQ

on the PCI Bus when it detects the PCI

Bus idle If BPe0 the PCEB takes responsibility for driving AD CBE

and PAR signals upon

detection of bus idle state After PCIRST

BPe0 (disabled)

Bus Lock (BL)

When BLe1 Bus Lock is enabled The arbiter considers the entire PCI Bus locked

upon initiation of any LOCKed transaction When BLe0 Resource Lock is enabled A LOCKed agent

is considered a LOCKed resource and other agents may continue normal PCI transactions After

PCIRST

BLe0 (disabled)

Guaranteed Access Time (GAT)

When GATe1 the PCEB is configured for Guaranteed Access

Time mode This mode guarantees the 21 ms CHRDY time-out specification for the EISAISA Bus

When the PCEB is a PCI initiator on behalf of an EISAISA master the PCI and main memory bus

(host) are arbitrated for in serial and must be owned before the EISAISA master is given ownership of

the EISA Bus If the PCEB is not programmed for Guaranteed Access Time (GATe0) the EISAISA

master is first granted the EISA Bus before the PCI Bus is arbitrated After a PCIRST

GATe0

(disabled)

319 ARBPRIPCI ARBITER PRIORITY CONTROL REGISTER

Address Offset

42h

Default Value

04h

Attribute

ReadWrite

Size

8 bits

This register controls the operating modes of the PCEB’s internal PCI arbiter The arbiter consists of four

arbitration banks that support up to six masters and three arbitration priority modesfixed priority rotating

priority and mixed priority modes See Section 54 PCI Bus Arbitration for details on programming and using

different arbitration modes

82375EB Datasheet(PDF) 34 Page - Intel Corporation

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