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82375EB Datasheet(PDF) 35 Page - Intel Corporation

Part # 82375EB
Description  PCI-EISA BRIDGE (PCEB)
PDF  131 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82375EB Datasheet(HTML) 35 Page - Intel Corporation

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82375EBSB
Bit
Description
7
Bank 3 Rotate Control
1eEnable 0eDisable
6
Bank 2 Rotate Control
1eEnable 0eDisable
5
Bank 1 Rotate Control
1eEnable 0eDisable
4
Bank 0 Rotate Control
1eEnable 0eDisable
32
Bank 2 Fixed Priority Mode Selectba
ba
00eBank0 l Bank3 l Bank1
10eBank3 l Bank1 l Bank0
01eBank1 l Bank0 l Bank3
11eReserved
1
Bank 1 Fixed Priority Mode Select
1eREQ3
l
CPUREQ
0eCPUREQ
l
REQ3
0
Bank 0 Fixed Priority Mode Select
1eREQ0
l
PCEBREQ
0ePCEBREQ
l
REQ0
Note
that PCEBREQ
is a PCEB internal signal
3110 ARBPRIXPCI ARBITER PRIORITY CONTROL EXTENSION REGISTER
Address Offset
43h
Default Value
00h
Attribute
ReadWrite
Size
8 bits
This register controls the fixed priority mode for bank 3 of the PCEB’s internal arbiter The ARBPRIX Register
is used in conjunction with the PCI Arbiter Priority Control (ARBPRI) Register
Bit
Description
71
Reserved
0
Bank 3 Fixed Priority Mode Select
1eREQ2
l
REQ1
0eREQ1
l
REQ2
3111 MCSCONMEMCS
CONTROL REGISTER
Address Offset
44h
Default value
00h
Attribute
ReadWrite
Size
8 bits
The MCSCON Register provides the master enable for generating MEMCS
This register also provides read
enable (RE) and write enable (WE) attributes for two main memory regions (the 512 KByte - 640 KByte region
and an upper BIOS region) PCI accesses within the enabled regions result in the generation of MEMCS
Note that the 0-512 KByte region does not have RE and WE attribute bits The 0-512 KByte region can only be
disabled with the MEMCS
Master Enable bit (bit 4) Note also that when the RE and WE bits are both 0 for a
particular region the PCI master can not access the corresponding region in main memory (MEMCS
is not
generated for either reads or writes)
35



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