Layout guidelines

AN3115

24/28

Doc ID 16830 Rev 3

3.2

PCB Thermal managing

The LNBH23L power dissipation inside the IC is mainly due to the DC-DC integrated

MOSFET power loss plus the linear regulator power dissipation. The total power dissipation

calculated, considering both the DC-DC and linear regulator power loss at the maximum

generated due to this power dissipation level requires a suitable heat-sink to keep the

junction temperature below the over temperature protection threshold at the rated ambient

temperature inside the set-top box.

For example: assuming a 70 °C max for the ambient temperature inside the STB case and a

°C/W.

on thermal resistance tests performed on the LNBH23L ST demonstration board, this result

is achievable with a minimum of a 4x4 cm² copper area placed just below the IC body (see

Figure 17

). Better performance with a smaller copper area may be achievable using four

layers (2s2p) PCB.

Usually the copper area is obtained by using the ground layer of a multi-layer PCB soldered

below the IC exposed pad. In Figure 14 an example of a layout for the QFN32 package with

a dual layer PCB is shown, where the IC exposed pad is connected to the ground layer and

the square dissipating area is thermally connected through 9 via holes filled by solder.

The best thermal and electrical performance can be achieved when an array of copper vias

barrel plating is incorporated in the land pattern at 1.2 mm grid. It is also recommended that

the via diameter should be 0.30 mm to 0.33 mm with 1 oz copper via barrel plating.

If the copper plating does not plug the vias, a solder mask material must be used to cap the

vias with a dimension equal to the via diameter + 0.1 mm minimum. This prevents the solder

from not being well spread through the thermal via and potentially creating a solder void

between the package bottom and the ground plane of the PCB.

Taking into account that the solder mask diameter should be at least 0.1 mm larger than the

via diameter.

Figure 17.

Typical junction to ambient thermal resistance with dual layer PCB, 1oz, 9 thermal

vias

0

10

20

30

40

50

60

70

80

0

2

4

6

8

1012

1416

Copper Area (cm²)