AN4149 datasheet(7/43 Pages) STMICROELECTRONICS

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AN4149

CCM PFC using FOT control

and the switching frequency will be:

Equation 7

The timing capacitor CT, therefore, will be selected with the following design formula:

Equation 8

Vout and fsw are design specifications, KP is chosen so that the voltage on pin MULT is

within the multiplier's linearity range (0 to 3 V) and ITIMER is specified in the "Electrical

characteristics" section of the L4984D datasheet.

Along a line half-cycle, TOFF goes all the way from nearly zero to the maximum on the

sinusoid peak. It is important to check that the OFF-time occurring on the peak of the

sinusoidal voltage at minimum input voltage is greater than the minimum programmable

value:

Equation 9

This constraint limits the maximum programmable frequency at:

Equation 10

As the line RMS voltage is increased and/or the output load is decreased the boost inductor

current tends to become discontinuous starting from the region around the zero-crossings.

As a result, in the DCM regions the switching frequency is no longer constant and tends to

increase.

Figure 6. Boundary between DCM and CCM

Vout

TIMER

Vout

1.2

min

TIMER

min

OFF

Vpk

Vout

Vpk

min

max

833

[]

KHz

AM13305v1

AN4149 Datasheet(PDF) 7 Page - STMicroelectronics