| Electronic Components Datasheet Search |
|
AN4149 Datasheet(PDF) 11 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
AN4149 Datasheet(HTML) 11 Page - STMicroelectronics |
|
11 / 43 page ![]() DocID023523 Rev 2 11/43 AN4149 Designing a CCM FOT-controlled PFC Expected power factor: Equation 19 Because of the narrow loop voltage bandwidth of the E/A to reject the ripple at twice the line frequency on the E/A output, the PFC output may experience overvoltage at startup or during load transients. In order to protect the controller from excessive output voltage that can overstress the output components and the load, in the L4984D a pin (PFC_OK, pin #6) has been dedicated to monitor the output voltage with a separate resistor divider. The divider is selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value (VOVP) larger than the maximum Vout that can be expected, also including worst-case load/line transients. Maximum output voltage (Vdc): Equation 20 The output voltage has a ripple Vout at twice the line frequency (2fL), and whose amplitude is proportional to the load and depends on the impedance of the output capacitor. The ripple amplitude determines the AC current flowing into the output capacitor and the ESR. The value of the maximum output voltage ripple accepted should be below a certain level to keep the output voltage far from the VOVP limit during normal operating conditions, to increase hold-up time, and to reduce the AC losses on the output capacitor. The peak-to- peak voltage ripple Vout is usually selected in the range between 2-8% of the output voltage. Here a ratio of 5% is chosen for the output voltage ripple, that is 20 V. Maximum output low frequency ripple (peak-to-peak): Equation 21 The desired ripple on the output voltage is not the only parameter used to select the bulk capacitor. The hold-up time, if requested, should also be taken into account. The hold-up time is defined as the duration of time that a power supply's output will remain above a minimum level in case of mains dips. The hold-up time (t Hold) is measured from the time when the line voltage disappears to the time when the output voltage reaches the required minimum voltage value (Voutmin). A hold- up time of 10-20 ms is often required for today’s offline power supplies. Values of 300 V and 15 ms for the minimum output voltage after line drop and hold-up time, respectively, are chosen here: Minimum output voltage after line drop (Vdc): Equation 22 Hold-up time (ms): Equation 23 99 . 0 = PF V V OVP 430 = V V out 20 = Δ V V out 300 min = ms t Ho l d 15 = |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |