AN2014 datasheet(15/65 Pages) STMICROELECTRONICS

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AN2014

EEPROM cell and memory array architecture

Consider, by way of example, the stress induced on the array elements when programming

one single byte in a 1Kbit EEPROM, organized as 128 x8 bit. The memory array is

composed of 8 pages (or rows) of 16 bytes (or columns).

Erase cycle: the complete row (page) that contains the addressed byte receives the VPP

signal, on the selected Row-line, as does the complete column, on the selected Cg-line:

•

Control Gates of all the Select transistors in the given row: 1 row x 16 bytes x 8 bits

=128

•

Control Gates of all the Control Gate transistors in the given row: 1 row x 16 bytes = 16

•

Drains of all the Control Gate transistors that are connected to the given Cg-line: 1

column x 8 rows = 8

The Bit-lines of the addressed bytes are floating.

Write cycle: the complete row (page) that contains the addressed byte receives the VPP

signal, on the selected Row-line:

•

Control Gates of all the Select transistors in the given row: 1 row x 16 bytes x 8 bits

=128

•

Control Gates of all the Control Gate transistors in the given row: 1 row x 16 bytes = 16

•

The Cg-line of the addressed byte is held at ground voltage

•

The Bit-lines are left floating or receive VPP depending on data to be written. The worst

case is when FFh is to be written, and all Bit-lines receive the VPP signal

•

Drains of all the Select transistors sharing the same 8 Bit-lines: 1 column x 8 rows x 8

bits = 64

This example shows how one single byte, being erased or programmed, incurs a lot of High

Voltage stress on elements that share the same row, column and bit-line as the one

addressed. For a 1Kbit EEPROM, programming one single byte to FFh induces stress on

128 Select transistors and 24 Control Gate transistors during auto-erase, and 192 Select

transistors and 16 Control Gate transistors during the write cycle, even though only 17

transistors (8 Select transistors, 8 FLOTOX transistors, 1 MOS transistor) were really being

addressed for the data change.

The bigger the memory array, the larger the number of additional transistors that are

involved. This is why when high cycling performance is required, it is recommended to

group N contiguous bytes inside one page and use the write page mode so that the overall

number of write cycles remains to its lowest value.

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