AN2476 datasheet(21/49 Pages) STMICROELECTRONICS

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AN2476

Power supply and clocks

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Power Consumption in STOP mode

Table 4 gives an approximate indication of the power savings that can be gained using the

LP_PARAM15:13 bits in the Power Management Control register (MRCC_PWRCTRL).

When all the LP_PARAM bits are enabled, the MCU power consumption consists only of the

static consumption of the Low Power Regulator (and the RSM) plus the leakage currents of

the digital logic (a total of 20µA typical at TA= 25° C for 3.3 V supply).

In dual supply mode (VREG_DIS pin=1), the power consumption consists only of the

leakage current (10 µA typical at TA = 25° C on V18 supply).

Note:

The Low Power RC Oscillator (LPOSC) and the 32.768kHz crystal oscillator (OSC32K) are

still active if previously programmed (RTC is still working if clocked by one of these two

clocks).

The ADC or USB can also consume power unless they are disabled before entering STOP

mode.

Wake-up events

Wake-up from STOP mode can be triggered by a reset, an external interrupt event or an

RTC alarm or NCKDF (no clock detected) interrupt. Refer to Table 3: STOP mode

functionality on page 20.

It is also possible to wake-up from STOP mode triggered by an external interrupt line

(configured in the EXTIT registers) without having enabled the corresponding IRQ in the

EIC. In this case, the External Interrupt Event will exit from STOP, but no IRQ routine will be

invoked. The program will simply resume execution.

The user program must clear the external interrupt line pending bit in the Pending Register

(EXTIT_PR) which caused the wake-up from STOP mode. If this pending bit is not cleared,

the next STOP mode entry procedure will be ignored and program execution will continue.

The RTC can wake up the MCU from STOP mode only through external interrupt line #15

which is internally connected to the RTC alarm. In this case, this external interrupt must be

properly configured. Note that only the RTC alarm is connected to external interrupt line #15

(not the RTC second or overflow interrupt).

Wake-up latency

When the OSC4M oscillator, the Flash memory and the MVREG voltage regulator are kept

active, the application is able to restart immediately with almost no latency.

If Flash memory is disabled in STOP Mode, using the LP_PARAM14 bit in the Power

Management Control register (MRCC_PWRCTRL), latency occurs when restarting due to

the Flash start-up time. Wait states are inserted until the Flash is ready. This latency is not

deterministic and may vary, depending on temperature or process dispersion.

Table 4.

Typical power consumption of circuits controlled by LP mode parameters

Control bit

Circuit

Power Consumption Saving

(under typical conditions

with 3.3V single power scheme)

LP_PARAM15

OSC4M oscillator and PLL

1.8 mA

LP_PARAM14

Flash memory

515 µA

LP_PARAM13

MVREG Main Voltage Regulator

130 µA

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