AN2784 datasheet(12/31 Pages) STMICROELECTRONICS

12 / 31 page

Interfacing with a nonmultiplexed, asynchronous 16-bit NOR Flash memory

AN2784

12/31

Doc ID 14779 Rev 4

To have a correct configuration of the FSMC timings, the timings have to take into account:

●

the maximum read/write access time

●

the different internal FSMC delays

●

the different internal memory delays

Hence, we have:

((ADDSET + 1) + (DATAST + 1)) × tHCLK = max (tWC)

DATAST × HCLK = tWP

For read access, DATAST must verify:

DATAST

 (t

AVQV + tsu(Data_NE) + tv(A_NE))/tHCLK – ADDSET – 4

Table 3 gives the meanings and values of the NOR Flash memory parameters.

Using the memory timings in Table 3 and the STM32F10xCDE FSMC asynchronous timings

in Table 2, we can compute the following values:

●

For the M29W128 NOR Flash memory, the timings are:

–

Address setup time: 0x0

–

Data setup time: 0x5

●

For the S29GL128P NOR Flash memory, the timings are:

–

Address setup time: 0x2

–

Data setup time: 0x5

Note:

The S29GL128P NOR Flash memory timings are also valid for the M29W128 NOR Flash

memory.

Table 3.

NOR Flash memory timings

Symbols

Parameter

Value

Unit

M29W128xx70

S29GL128P90

tWC

Address valid to next address valid for write

operation

tRC

Address valid to next address valid for read

access

tWP

Write Enable low to Write Enable high

tAVQV

Address valid to output valid

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