AN2784 datasheet(24/31 Pages) STMICROELECTRONICS

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Interfacing with an 8-bit NAND Flash memory

AN2784

24/31

Doc ID 14779 Rev 4

Based on the NAND Flash memory access timings shown in Figure 4, the following

equations are found:

●

The write or read access time is the time between the falling edge and the rising edge

of the NAND Flash memory Chip Select signal. It is computed as a function of the

FSMC timing parameter:

((SET + 1) + (WAIT + 1) + (HOLD + 1)) × tHCLK  Write/Read access

●

The Wait time is measured between the falling edge and the rising edge of the

Write/Read Enable signal:

Write/Read Enable signal low to high = (WAIT + 1) × tHCLK

●

For write access, the HIZ parameter is the time measured between the falling edge of

the Chip Select signal and the data setup on bus:

(HIZ+1) x tHCLK  Chip Select setup time to Data setup.

●

The HOLD timing is given in the NAND datasheet as follows:

(HOLD +1) x tHCLK = Write Enable High to Chip Enable / Address/Command Latch

High

To make sure of the correct timing configuration of the FSMC, the timings have to take into

consideration:

●

The maximum read/write access time

●

The different internal FSMC delays

●

The different internal memory delays

Hence, we have the following equations following the NAND512W3A NAND datasheet:

●

(SET + 1) x tHCLK  max (tCS, tCLS, tALS, tCLR, tAR) - tWP

●

(WAIT + 1) x tHCLK  max (tWP,tRP)

●

(HIZ + 1) x tHCLK  max(tCS, tALS, tCLS) + (tWP - tDS)

●

(HOLD + 1) x tHCLK  max (tCH, tCLH, tALH)

●

((WAIT + 1) + ( HOLD + 1) + (SET + 1)) x tHCLK  max (tWC/RC)

Considering the different timings in the FSMC and the memory, the equations become:

●

WAIT must verify:

(WAIT + 1)× tHCLK  (tREA + tsu(D-NOE))

WAIT

 (t

REA + tsu(D-NOE)) /tHCLK - 1

Note:

tsu(D-NOE) is specified in the STM32F10xCDE datasheet.

tsu(D-NOE) = 25 ns

Table 7 gives the meanings and values of the NAND512W3A2C memory parameters.

Table 7.

NAND512W3A2C Flash memory timings

Symbol

Parameter

Value

Unit

tCEA

Chip Enable low to output valid

tWP

Write Enable low to Write Enable high

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