AN2784 datasheet(30/31 Pages) STMICROELECTRONICS

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Revision history

AN2784

30/31

Doc ID 14779 Rev 4

Revision history

Table 11.

Document revision history

Date

Revision

Changes

22-Jul-2008

Initial release.

19-Sep-2008

Cellular RAM, OneNAND and COSMORAM references removed.

NWAIT signal removed from Figure 3: Asynchronous NOR Flash

read access timing, Figure 4: Asynchronous NOR Flash write access

timing, Figure 5: 16-bit NOR Flash: M29W128FL/GL connection to

STM32F10xxx, Figure 6: SRAM asynchronous read access timing

and Figure 7: SRAM asynchronous write access timing.

Note modified in Section 2.3: Hardware connection. Table 10: NOR

Flash memory connection to the FSMC modified.

Note added to Section 2.2: Timing computation.

Small text changes.

07-Apr-2009

Figure 1: FSMC block diagram corrected.

tsu(Data_NE) and tv(A_NE) rows removed and tsu(Data_NE) + tv(A_NE)

value modified in Table 2: STM32F10xCDE FSMC asynchronous

timings.

Note: 1 on page 12 modified.

Data setup time modified in Section 2.2: Timing computation and

Section 3.2: Timing computation. Small text change in Section 4.1.1:

Typical use of the FSMC to interface with a NAND memory.

Small text changes.

07-Jun-2010

Updated Section 1: Overview of the STM32F10xxx flexible static

memory controller

Added Section 1.1: Interfacing asynchronous static memories (NOR

Flash, SRAM)

Modified Section 2.1: FSMC configuration

Updated Section 2.2: Timing computation

Updated Section 2.3: Hardware connection

Updated Section 3.2: Timing computation

Updated Section 4.2: Timing computation

Updated Section 5.2: Interfacing the FSMC with a NOR Flash

memory

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