AN3422 datasheet(18/52 Pages) STMICROELECTRONICS

18 / 52 page

Peripheral migration

AN3422

18/52

Doc ID 018976 Rev 2

HSE

3 - 25 MHz

Depending on the product line

used

1 - 24 MHz

No change to SW configuration:

– Enable/disable

RCC_CR[HSEON]

– Status flag

RCC_CR[HSERDY]

LSE

32.768 kHz

LSE configuration/status bits are

now in RCC_CSR register.

– Enable/disable

RCC_CSR[LSEON]

– Status flag

RCC_CSR[LSERDY]

In L1 series the LSEON and

LSERDY bits occupy bits

RCC_CSR[9:8] respectively

instead of bit RCC_BDCR[1:0] in

F1 series.

PLL

– Connectivity line: main PLL +

2 PLLs for I2S, Ethernet and

OTG FS clock

– Other product lines: main

PLL

– Main PLL for system

There is no change to PLL

enable/disable

RCC_CR[PLLON] and status

flag RCC_CR[PLLRDY].

However, PLL configuration

(clock source selection,

multiplication/division factors)

are different. In L1 series

dedicated bits

RCC_CFGR[PLLDIV] are used

to configure the PLL divider

parameters and the PLL

multiplication factors are

different. The PLL sources are

only HSI and HSE.

System clock

source

HSI, HSE or PLL

MSI, HSI, HSE or PLL

No change to SW configuration:

– Selection bits

RCC_CFGR[SW]

– Status flag RCC_CFGR[SWS]

However there is one more

source, MSI, and the selection

bit meanings are different.

System clock

frequency

up to 72 MHz depending on the

product line used

8 MHz after reset using HSI

32 MHz

2 MHz after reset using MSI

For STM32L1 Flash wait states

should be adapted according to

the system frequency, the

product voltage range VCORE

and the supply voltage range

VDD.

AHB

frequency

up to 72 MHz

up to 32 MHz

No change to SW configuration:

configuration bits

RCC_CFGR[HPRE]

Table 5.

RCC differences between STM32F1 and STM32L1 series (continued)

RCC main

features

STM32F1 series

STM32L1 series

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