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AN3422 Datasheet(PDF) 20 Page - STMicroelectronics |
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AN3422 Datasheet(HTML) 20 Page - STMicroelectronics |
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20 / 52 page ![]() Peripheral migration AN3422 20/52 Doc ID 018976 Rev 2 In addition to the differences described in the table above, the following additional adaptation steps may be needed for the migration: 1. Performance versus VCORE ranges: The maximum system clock frequency and FLASH wait state depends on the selected voltage range VCORE and also on VDD. The following table gives the different clock source frequencies depending on the product voltage range. 2. System clock configuration: when moving from F1 series to L1 series only a few settings need to be updated in the system clock configuration code; mainly the Flash settings (configure the right wait states for the system frequency, prefetch Internal oscillator measurement / calibration – LSI connected to TIM5 CH4 IC: can measure LSI w/ respect to HSI/HSE clock – LSI connected to TIM10 CH1 IC: can measure LSI w/ respect to HSI/HSE clock – LSE connected to TIM10 CH1 IC: can measure LSE w/ respect to HSI/HSE clock – HSE connected to TIM11 CH1 IC: can measure HSE w/ respect to LSE/HSI clock – MSI connected to TIM11 CH1 IC: can measure MSI range w/ respect to HSI/HSE clock There is no configuration to perform in RCC registers. Interrupt – CSS (linked to NMI IRQ) – LSIRDY, LSERDY, HSIRDY, HSERDY, PLLRDY, PLL2RDY and PLL3RDY (linked to RCC global IRQ) – CSS (linked to IRQ) – LSIRDY, LSERDY, MSIRDY, HSIRDY, HSERDY and PLLRDY (linked to RCC global IRQ) No change to SW configuration: interrupt enable, disable and pending bits clear are done in RCC_CIR register. Table 5. RCC differences between STM32F1 and STM32L1 series (continued) RCC main features STM32F1 series STM32L1 series Comments Table 6. Performance versus VCORE ranges CPU performance Power performance VCORE range Typical Value (V) Max frequency (MHz) VDD range 1 WS 0 WS High Low 1 1.8 32 16 2.0 - 3.6 Medium Medium 2 1.5 16 8 1.65 - 3.6 Low High 3 1.2 4 2 |
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