AN4228 datasheet(37/90 Pages) STMICROELECTRONICS

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AN4228

Firmware migration using the library

used to configure the microcontroller system at start-up and before branching to the main()

program.

Note:

For STM32F3xx, you can use the clock configuration tool,

STM32F3xx_Clock_Configuration.xls, to generate a customized SystemInit() function

depending on your application requirements. For more information, refer to AN4152 “Clock

configuration tool for STM32F30xx microcontrollers” and to AN4132 Clock configuration tool

for STM32F37xx microcontrollers”.

4.2.2

Peripheral access configuration

As presented in Section 3.4: Reset and clock controller (RCC) interface, you need to call

different functions to enable/disable the peripheral clock or enter/exit from reset mode.

As an example, GPIOA is mapped on AHB bus on STM32F3 series (APB2 bus on

STM32F1 series). To enable its clock in the STM32F1 series, use

_AHBPeriphClockCmd(_AHBPeriph_GPIOA, ENABLE)

instead of:

_APB2PeriphClockCmd(_APB2Periph_GPIOA, ENABLE);

Refer to Table 8 for the peripheral bus mapping changes between STM32F3 and STM32F1

series.

4.2.3

Peripheral clock configuration

Some STM32F3xx peripherals support dual clock features. The table below summarizes the

clock sources for these IPs in comparison with STM32F10x peripherals.

Table 19. STM32F10x and STM32F3xx clock source API correspondence

Peripherals

Source clock in STM32F10x

Source clock in STM32F3xx

CEC

APB1 clock with prescaler

– HSI/244: by default

–LSE

– APB clock: Clock for the digital interface

(used for register read/write access). This

clock is equal to the APB2 clock.

I2C

APB1 clock

I2C can be clocked with:

– System clock

–HSI

SPI/I2S

System clock

– APB clock

– External clock for I2S clock source(1)

It is applicable only for STM32F30xx devices.

USART

– USART1 can be clocked by PCLK2

(72 MHz Max)

– Other USARTs can be clocked by

PCLK1 (36 MHz Max)

USART can be clocked with:

– system clock

– LSE clock

– HSI clock

– APB clock (PCLK)

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