UPD75P218KB datasheet(24/36 Pages) NEC

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µPD75P218

Data Memory STOP Mode Low Voltage Data Retention Characteristics (Ta = –40 to +70 ˚C)

Parameter

Data retention voltage

Data retention current Note 1

Release signal SET time

Oscillation stabilization time Note 2

Unit

µA

µs

MAX.

6.0

TYP.

0.1

217/fx

Note 3

MIN.

2.0

Conditions

VDDDR = 2.0 V

Release by RESET input

Release by interrupt request

Symbol

VDDDR

IDDDR

tSREL

tWAIT

Notes 1. Does not include pull-down resistor current.

2. The oscillation stabilization WAIT time is the time during which the CPU operation is stopped to

prevent unstable operation while the oscillation is started.

3. The WAIT time depends on the setting of the basic interval timer mode register (BTM) according to

the following table.

BTM3

BTM2

BTM1

BTM0

–

000

–

011

–

101

–

111

WAIT time

(fXX = 6.0 MHz)

(fXX = 4.19 MHz)

220/fXX (approx. 175 ms)

220/fXX (approx. 250 ms)

217/fXX (approx. 21.8 ms)

217/fXX (approx. 31.3 ms)

215/fXX (approx. 5.46 ms)

215/fXX (approx. 7.82 ms)

213/fXX (approx. 1.37 ms)

213/fXX (approx. 1.95 ms)

Data Retention Timing (STOP mode is released by RESET input)

Data retention mode

STOP mode

VDDDR

tSREL

tWAIT

Internal reset

operation

HALT mode

Operation

mode

Execution of

STOP instruction

VDD

RESET

Data Retention Timing (STOP mode is released by interrupt signal)

Data retention mode

STOP mode

VDDDR

tSREL

tWAIT

HALT mode

Operation

mode

Execution of

STOP mode

VDD

Standby release signal

(Interrupt request)

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