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UPD75P218KB Datasheet(PDF) 20 Page - NEC |
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UPD75P218KB Datasheet(HTML) 20 Page - NEC |
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20 / 36 page  20 µPD75P218 Conditions Main system clock Subsystem clock VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V Parameter Note 1 CPU clock cycle time (minimum instruction execu- tion time = 1 machine cycle) TI0 input frequency TI0 input low- and high-level width SCK cycle time SCK low- and high-level width SI setup time (to SCK ↑) SI hold time (from SCK ↑) SCK ↓ → SO output delay time Interrupt inputs low- and high-level width RESET low-level width AC Characteristics (Ta = –40 to +70 ˚C, V DD = 2.7 to 6.0 V) MAX. 32 32 125 0.6 165 300 1000 Unit µs µs µs MHz kHz µs µs µs µs µs µs µs ns µs ns ns ns ns ns µs µs µs µs TYP. 122 MIN. 0.67 2.6 114 0 0 0.83 3 0.8 0.95 3.2 3.8 0.4 tKCY/2–50 1.6 tKCY/2–150 100 400 Note 2 2tCY 10 10 Symbol tCY fTI tTIH, tTIL tKCY tKH, tKL tSIK tKSI tKSO tINTH, tINTL tRSL VDD = 4.5 to 6.0 V Input Output Input Output Input Output Input Output INT0 INT1 INT2,4 |
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