UPD75P218KB datasheet(17/36 Pages) NEC

17 / 36 page

µPD75P218

Main System Clock Configurations (Ta = –40 to +70 ˚C, V DD = 2.7 to 6.0 V)

Resonator

Ceramic

resonator

Crystal

resonator

External

clock

Recommended constants

Parameter

Note 1

Oscillation (fXX)

frequency

Note 2

Oscillation

stabilization time

Note 1

Oscillation

frequency (fXX)

Note 2

Oscillation

stabilization time

Note 1

X1 input fre-

quency (fX)

X1 input high-

and low-level

width (tXH, tXL)

Conditions

VDD = Oscillator

operating

voltage

range

After VDD reaches

the minimum

oscillator operat-

ing voltage range

VDD = 4.5 to 6.0 V

MIN.

2.0

TYP.

4.19

MAX.

6.2

250

Unit

MHz

Subsystem Clock Configurations (Ta = –40 to +70 ˚C, V DD = 2.7 to 6.0 V)

Resonator

Crystal

resonator

External

clock

Recommended constants

Parameter

Note 1

Oscillation

frequency (fXT)

Note 2

Oscillation

stabilization time

XT1 input

frequency (fXT)

XT1 input high-

and low-level

width (tXTH, tXTL)

Conditions

VDD = 4.5 to 6.0 V

MIN.

TYP.

32.768

1.0

MAX.

100

Unit

kHz

µs

Notes 1. The oscillator frequency and input frequency indicate only the oscillator characteristics.

Refer to the AC Characteristics for the instruction execution time.

2. The oscillation stabilization time is the time required for the oscillation to stabilize after VDD is applied

and reaches the VDD spec or after STOP mode is released.

Capacitance (Ta = 25 ˚C, V DD = 0 V)

MIN.

Symbol

CIN

COUT

CIO

Unit

MAX.

TYP.

Conditions

f = 1 MHz

Unmeasured pins returned to 0 V

Parameter

Input capacitance

Output

capacitance

Input/Output capacitance

Other than

display output

Display output

mPD74HCU04

XT1

XT2

330 kW

XT1

XT2

Open

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