DP83867CS datasheet(20/114 Pages) TI1

20 / 114 page

DP83867CS, DP83867IS, DP83867E

SNLS504 – OCTOBER 2015

www.ti.com

Feature Description (continued)

9.3.1.2 Magic Packet Example

The following is an example Magic Packet for a Destination Address of 11h 22h 33h 44h 55h 66h and a

SecureOn Password 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh:

DESTINATION SOURCE MISC FF FF FF FF FF FF 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22

33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66

11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44

55 66 11 22 33 44 55 66 2A 2B 2C 2D 2E 2F MISC CRC

9.3.1.3 Wake on LAN Configuration and Status

Wake on LAN functionality is configured via the RXFCFG register (address 0x0134). Wake on LAN status is

reported in the RXFSTS register (address 0x0135).

9.3.2 Start of Frame Detect for IEEE1588 Time Stamp

The DP83867 supports an IEEE 1588 indication pulse at the SFD (start frame delimiter) for the receive and

transmit paths. The pulse can be delivered to various pins. The pulse indicates the actual time the symbol is

presented on the lines (for transmit), or the first symbol received (for receive). The exact timing of the pulse can

be adjusted via register. Each increment of phase value is an 8ns step.

Figure 10. IEEE 1588 Message Timestamp Point

The SFD pulse output can be configured using the GPIO Mux Control registers, GPIO_MUX_CTRL1 (register

address 0x0171) and GPIO_MUX_CTRL2 (register address 0x0172). The ENHANCED_MAC_SUPPORT bit in

RXCFG (register address 0x0134) must also be set to allow output of the SFD.

9.3.3 Clock Output

The DP83867 has several internal clocks, including the local reference clock, the Ethernet transmit clock, and the

Ethernet receive clock. An external crystal or oscillator provides the stimulus for the local reference clock. The

local reference clock acts as the central source for all clocking in the device.

The local reference clock is embedded into the transmit network packet traffic and is recovered from the network

packet traffic at the receiver node. The receive clock is recovered from the received Ethernet packet data stream

and is locked to the transmit clock in the partner.

Using the I/O Configuration register (address 0x0170), the DP83867 can be configured to output these internal

clocks via the CLK_OUT pin. By default, the output clock is synchronous to the X_I oscillator / crystal input. The

default output clock is suitable for use as the reference clock of another DP83867 device. Via registers, the

output clock can be configured to be synchronous to the receive data at the 125-MHz data rate or at the divide

by 5 rate of 25 MHz. It can also be configured to output the line driver transmit clock. When operating in

1000Base-T mode, the output clock can be configured for any of the four transmit or receive channels.

The output clock can be disabled using the CLK_O_DISABLE bit of the I/O Configuration register.

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DP83867CS Datasheet(PDF) 20 Page - Texas Instruments