DP83867CS datasheet(56/114 Pages) TI1

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DP83867CS, DP83867IS, DP83867E

SNLS504 – OCTOBER 2015

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9.6.10 1000BASE-T Configuration Register (CFG1)

Table 20. Configuration Register 1 (CFG1), Address 0x0009

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:13

TEST MODE

000, RW

Test Mode Select:

111 = Test Mode 7 - Repetitive {Pulse, 63 zeros}

110 = Test Mode 6 - Repetitive 0001 sequence

101 = Test Mode 5 - Scrambled MLT3 Idles

100 = Test Mode 4 - Transmit Distortion Test

011 = Test Mode 3 - Transmit Jitter Test (Slave Mode)

010 = Test Mode 2 - Transmit Jitter Test (Master Mode)

001 = Test Mode 1 - Transmit Waveform Test

000 = Normal Mode

MASTER / SLAVE MANUAL

0, RW

Enable Manual Master / Slave Configuration:

CONFIGURATION

1 = Enable Manual Master/Slave Configuration control.

0 = Disable Manual Master/Slave Configuration control.

Using the manual configuration feature may prevent the PHY from

establishing link in 1000Base-T mode if a conflict with the link

partner’s setting exists.

MASTER / SLAVE

0, RW

Manual Master / Slave Configuration Value:

CONFIGURATION VALUE

1 = Set PHY as MASTER when register 09h bit 12 = 1.

0 = Set PHY as SLAVE when register 09h bit 12 = 1.

Using the manual configuration feature may prevent the PHY from

establishing link in 1000Base-T mode if a conflict with the link

partner’s setting exists.

PORT TYPE

0, RW

Advertise Device Type: Multi or single port:

1 = Multi-port device.

0 = Single-port device.

100BASE-T FULL DUPLEX

0, RW

Advertise 1000BASE-T Full Duplex Capable:

1 = Advertise 1000Base-T Half Duplex ability.

0 = Do not advertise 1000Base-T Half Duplex ability.

1000BASE-T HALF DUPLEX

0, RW

Advertise 1000BASE-T Half Duplex Capable:

1 = Advertise 1000Base-T Half Duplex ability.

0 = Do not advertise 1000Base-T Half Duplex ability.

TDR AUTO RUN

0, RW

Automatic TDR on Link Down:

1 = Enable execution of TDR procedure after link down event.

0 = Disable automatic execution of TDR.

6:0

RESERVED

000 0000, RO

RESERVED: Write ignored, read as 0.

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