DP83867CS datasheet(81/114 Pages) TI1

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DP83867CS, DP83867IS, DP83867E

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SNLS504 – OCTOBER 2015

9.6.35 BIST Control and Status Register 1 (BICSR1)

Table 46. BIST Control and Status Register 1 (BICSR1), Address 0x0071

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:0

PRBS_BYTE_CNT

0x0000, RO

Holds the number of total bytes received by the PRBS checker.

Value in this register is locked when write is done to register

BICSR2 bit[0] or bit[1].

The count stops at 0xFFFF when PRBS_COUNT_MODE in BISCR

9.6.36 BIST Control and Status Register 2 (BICSR2)

Table 47. BIST Control and Status Register 2 (BICSR2), Address 0x0072

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:11

Reserved

0x00, RO

Ignored on Read

PRBS Checker Packet Count Overflow

If set, PRBS Packet counter has reached overflow. Overflow is

PRBS_PKT_CNT_OVF

0, RO

cleared when PRBS counters are cleared by setting bit #1 of this

PRBS Byte Count Overflow

PRBS_BYTE_CNT_OVF

0, RO

If set, PRBS Byte counter has reached overflow. Overflow is cleared

when PRBS counters are cleared by setting bit #1 of this register.

Reserved

0,RO

Ignore on Read

Holds number of error bytes that are received by PRBS checker.

Value in this register is locked when write is done to bit[0] or bit[1]

When PRBS Count Mode set to zero, count stops on 0xFF (see

7:0

PRBS_ERR_CNT

0x00, RO

Notes: Writing bit 0 generates a lock signal for the PRBS counters.

Writing bit 1 generates a lock and clear signal for the PRBS

counters

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