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L9662 Datasheet(PDF) 56 Page - STMicroelectronics

Part # L9662
Description  Octal squib driver and quad Manchester/PSI5 encoded sensor
PDF  80 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L9662 Datasheet(HTML) 56 Page - STMicroelectronics

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Functional description
L9662
56/80
DocID028325 Rev 1
Figure 10. Transmission in asynchronous mode
High voltage mode and satellite SYNC mode
In High Voltage Mode and SYNC Mode the ICHx outputs are regulated to a higher output
voltage (VICHx_HV) than in Receive mode. In this case, the channel power supply is taken
from a separate input pin (VSYNC). Both modes are activated and deactivated by the same
SPI command. The start of the SYNC impulse is arbitrary and is created by a signal from the
μC using the INITSYNC input pin. The Sync pulse shall be initiated for all satellites based on
the rising edge of the INITSYNC input after a tSYNCDLY delay. The duration of the sync pulse
shall be based on the programmed sync pulse high time based on [D9:D8] in the MCR. If
the sync timing register has not been written the default pulse high time shall be tSYNC_high1.
The absence of an INITSYNC input rising edge does not prevent processing of incoming
messages when in HV or SYNC mode.
For Sync mode the valid sync time selections would be tSYNC_high1 and tSYNC_high2. For
High Voltage Mode the valid sync time selections would be tSYNC_high3 and tSYNC_high4. The
time selections of tSYNC_high3 and tSYNC_high4 cannot be used in normal operation because
the time duration will be longer than the receive disable time, resulting in improper
communication with the satellites. For HV mode (used only in the manufacturing or supplier
facility) if there is a short to battery flag is set then the message must be ignored.
At the start of a sync pulse there is a short period before the actual start of the sync pulse for
a channel where the current is limited to 20mA typical. This low current limit will start after
the tINITSYNCFLT time and last for 200 ns. The satellite current requirements in conjunction
with the capacitance on the pins should be verified so that the minimum satellite voltage can
be maintained.
SYNC mode
During the receiver disable time a sync pulse cannot be initiated and any change on the
INITSYNC pin will be ignored by the ASIC.The satellite SYNC mode is used to generate
automatic sync pulses for synchronous data transmission. In this mode, the output operates
in Receive Mode, but is periodically switched to a higher output voltage VICHx_HV. Thus, the
receiver decoder blocks are deactivated for the duration of the Sync pulse. To avoid
disturbance in the data flow during re-settling of the output voltage to the receive-mode
level, the receiver decoder block is deactivated for time tRECV_disable.



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