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L9662 Datasheet(PDF) 72 Page - STMicroelectronics |
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L9662 Datasheet(HTML) 72 Page - STMicroelectronics |
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72 / 80 page  Functional description L9662 72/80 DocID028325 Rev 1 0 = Checksum performed by ASIC 1 = Checksum calculation disabled Bits [D10:D09]. These bits are used to configure the number of bits in the MS and PSI5 Modes. MS Mode: For these bits to execute on any given channel, the channel has to be configured for generic protocol B / protocol A through bits <D13:D10> in the MCR register. If the checksum calculation is disabled the ASIC does not perform a parity check on the incoming message and will be included in the data field. PSI5 Mode: For these bits to execute on any given channel, the channel has to be configured for PSI5 - Parity protocol through bits <D13:D10> in the MCR register. In PSI5 mode, the checksum calculation is always done by the ASIC, thus, bit D11 is ignored and parity bits are not included in the MISO response. Bits [D7:D6]. These bits shall configure speed selection for any of the satellite channels. Upon power up or reset the protocol configuration shall initialize to the default speed as shown in the table below. Table 41. Protocol A/B mode configuration D10 D09 Protocol-A Mode (Set in MCR – D13:D10) Protocol -B Mode (Set in MCR – D13:D10) Message Length Data Report Length Message Length Data Report Length D11=0 D11=1 D11=0 D11=1 0 0 18 bits 13 bits (default) 16 bits 16 bits 13 bits (default) 14 bits) 0 1 16 bits 11 bits 14 bits 14 bits 11 bits 12 bits 1 0 15 bits 10 bits 13 bits 13 bits 10 bits 11 bits 1 1 13 bits 8 bits 11 bits 11 bits 8 bits 9 bits Table 42. PSI5 – parity protocol (Set in MCR D13:D10) D10 D09 Message Length Data Report 0 0 16 bits 13 bits (default) 0 1 14 bits 11 bits 1 0 13 bits 10 bits 1 1 11 bits 8 bits |
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