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AT90LS4433-4AI Datasheet(PDF) 32 Page - ATMEL Corporation |
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AT90LS4433-4AI Datasheet(HTML) 32 Page - ATMEL Corporation |
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32 / 126 page ![]() 32 AT90S/LS4433 1042H–AVR–04/03 Idle Mode When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle mode stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt sys- tem to continue operating. This enables the MCU to wake up from external triggered interrupts as well as internal ones like Timer Overflow interrupt and Watchdog Reset. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Sta- tus Register (ACSR). This will reduce power consumption in Idle mode. Power-down Mode When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power- down mode. In this mode, the External Oscillator is stopped while the external interrupts and the Watchdog (if enabled) continue operating. Only an External Reset, a Watchdog Reset (if enabled) or an external level interrupt can wake up the MCU. Note that if a level-triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for a time to wake up the MCU. This makes the MCU less sensitive to noise. The Wake-up period is equal to the clock-counting part of the Reset period (see Table 5). The MCU will wake up from Power-down if the input has the required level for two Watchdog Oscillator cycles. If the wake-up period is shorter than two Watchdog Oscillator cycles, the MCU will wake up if the input has the required level for the duration of the Wake-up period. If the wake-up condition disappears before the wake-up period has expired, the MCU will wake up from Power-down without executing the corresponding interrupt. The period of the Watchdog Oscillator is 2.7 µs (nominal) at 3.0V and 25 °C. The fre- quency of the Watchdog Oscillator is voltage dependent as shown in the Electrical Characteristics section. When waking up from Power-down mode, a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period. |
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