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AT90LS4433-4AI Datasheet(PDF) 50 Page - ATMEL Corporation |
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AT90LS4433-4AI Datasheet(HTML) 50 Page - ATMEL Corporation |
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50 / 126 page  50 AT90S/LS4433 1042H–AVR–04/03 pins are inputs. When SS is driven high, externally all pins are inputs and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is brought high. If the SS pin is brought high during a transmission, the SPI will stop sending and receiving immediately and both data received and data sent must be considered as lost. Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 38 and Figure 39. Figure 38. SPI Transfer Format with CPHA = 0 and DORD = 0 Figure 39. SPI Transfer Format with CPHA = 1 and DORD = 0 |
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