DS90C3202

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SNLS191D – APRIL 2005 – REVISED APRIL 2013

DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver

Check for Samples: DS90C3202

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FEATURES

DESCRIPTION

The DS90C3202 is a 3.3V single/dual FPD-Link 10-

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•

Up to 9.45 Gbit/s data throughput

bit color receiver is designed to be used in Liquid

•

8 MHz to 135 MHz input clock support

Crystal Display TVs, LCD Monitors, Digital TVs, and

•

Supports up to QXGA panel resolutions

Plasma Display Panel TVs. The DS90C3202 is

designed to interface between the digital video

•

Supports HDTV panel resolutions and frame

processor and the display device using the low-

rates up to 1920 x 1080p

power, low-EMI LVDS (Low Voltage Differential

•

LVDS 30-bit, 24-bit or 18-bit color data inputs

Signaling) interface. The DS90C3202 converts up to

•

Supports single pixel and dual pixel interfaces

ten LVDS data streams back into 70 bits of parallel

LVCMOS/LVTTL

data.

The

receiver

can

be

•

Supports spread spectrum clocking

programmed with rising edge or falling edge clock.

•

Two-wire serial communication interface

Optional wo-wire serial programming allows fine

•

Programmable clock edge and control strobe

tuning in development and production environments.

select

With an input clock at 135 MHz, the maximum

transmission rate of each LVDS line is 945 Mbps, for

•

Power down mode

an aggregate throughput rate of 9.45 Gbps (945

•

+3.3V supply voltage

Mbytes/s). This allows the dual 10-bit LVDS Receiver

•

128-pin TQFP Package

to support resolutions up to HDTV.

•

Compliant to TIA/EIA-644-A-2001 LVDS

Standard

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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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PRODUCTION DATA information is current as of publication date.

Copyright © 2005–2013, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.