DS99R101, DS99R102

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SNLS240D – MARCH 2007 – REVISED APRIL 2013

APPLICATIONS INFORMATION

USING THE DS99R101 AND DS99R102

The DS99R101/DS99R102 Serializer/Deserializer (SERDES) pair sends 24 bits of parallel LVCMOS data over a

serial LVDS link up to 960 Mbps. Serialization of the input data is accomplished using an on-board PLL at the

Serializer which embeds clock with the data. The Deserializer extracts the clock/control information from the

incoming data stream and deserializes the data. The Deserializer monitors the incoming clockl information to

determine lock status and will indicate lock by asserting the LOCK output high.

POWER CONSIDERATIONS

An all CMOS design of the Serializer and Deserializer makes them inherently low power devices. Additionally,

designs.

NOISE MARGIN

The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still

reliably recover data. Various environmental and systematic factors include:

For a graphical representation of noise margin, please see Figure 16.

TRANSMISSION MEDIA

The Serializer and Deserializer can be used in point-to-point configuration, through a PCB trace, or through

twisted pair cable. In a point-to-point configuration, the transmission media needs be terminated at both ends of

the transmitter and receiver pair. Interconnect for LVDS typically has a differential impedance of 100 Ohms. Use

cables and connectors that have matched differential impedance to minimize impedance discontinuities. In most

applications that involve cables, the transmission distance will be determined on data rates involved, acceptable

bit error rate and transmission medium.

LIVE LINK INSERTION

The Serializer and Deserializer devices support live pluggable applications. The “Hot Inserted” operation on the

serial interface does not disrupt communication data on the active data lines. The automatic receiver lock to

random data “plug & go” live insertion capability allows the DS99R102 to attain lock to the active data stream

during a live insertion event.

PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS

Circuit board layout and stack-up for the LVDS SERDES devices should be designed to provide low-noise power

feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to

minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly

improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane

capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at

high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass

capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the

range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the

tantalum capacitors should be at least 5X the power supply voltage being used.

Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per

supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power

entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is

recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors

connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external

bypass capacitor will increase the inductance of the path.

Copyright © 2007–2013, Texas Instruments Incorporated

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Product Folder Links: DS99R101 DS99R102