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LM3560TLX/NOPB Datasheet(PDF) 5 Page - Texas Instruments |
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LM3560TLX/NOPB Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 48 page ![]() LM3560 www.ti.com SNOSB43B – SEPTEMBER 2011 – REVISED AUGUST 2013 ELECTRICAL CHARACTERISTICS (1) (2) (continued) Limits in standard typeface are for TA = +25°C. Limits in boldface type apply over the full operating ambient temperature range ( −40°C ≤ TA ≤ +85°C). Unless otherwise specified, VIN = 3.6V, VHWEN = VIN. Symbol Parameter Test Conditions Min Typ Max Unit Time from when ADC Delay Register Bit [5] = 1 16 ILED hits target until tD µs ADC Delay Register Bit [5] = 0 VLED data is 250 ADC Delay Register Bits [4:0] = 0000 available VF_ADC ADC Threshold 3.0V ≤ VIN ≤ 4.2V, VLED Monitor Register Bits [3:0] = 1111 4.05 4.2 4.35 V HWEN, STROBE, TX1/TORCH/GPIO1, TX2/INT/GPIO2 Voltage Specifications VIL Input Logic Low 2.7V ≤ VIN ≤ 4.2V 0 0.4 V VIH Input Logic High 2.7V ≤ VIN ≤ 4.2V 1.2 VIN V Internal Pull Down RPD Resistance on TX1, 300 k Ω TX2, STROBE I2C-Compatible Voltage Specifications (SCL, SDA) VIL Input Logic Low 2.7V ≤ VIN ≤ 4.2V 0 0.4 V VIH Input Logic High 2.7V ≤ VIN ≤ 4.2V 1.2 VIN V Output Logic Low VOL ILOAD = 3mA, 2.7V ≤ VIN ≤ 4.2V 400 mV (SDA) I2C-Compatible Timing Specifications (SCL, SDA) (7), see Figure 42 SCL(Clock fSCL 0 400 kHz Frequency) 20ns + Rise Time of Both tRISE 0.1 × 300 ns SDA and SCL CBUS 20ns + Fall Time of Both tFALL 0.1 × 300 ns SDA and SCL CBUS Low Period of SCL tLOW 1.3 µs Clock High Period of SCL tHIGH 600 ns Clock Hold Time for Start tHD;STA (or Repeated 600 ns Start)Condition Set-up Time for a tSU;STA 600 ns Repeated Start tHD;DAT Data Hold Time 0 ns tSU;DAT Data Setup Time 100 ns Set-up Time for tSU;STO 600 ns Stop Condition tVD;DAT Data Valid Time 900 ns Data Valid tVD;ACK 900 ns Acknowledge Time Bus Free Time Between a Start tBUF 1.3 µs and a Stop Condition (7) Specified by design. Not production tested. Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM3560 |
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