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2016-01-0022

PT0553-4

02/15/16

10

PI4IOE5V9673

Preliminary Datasheet

16-bit I

Figure 8. Write Mode

Reading from a port (Input mode)

All ports programmed as input should be set to logic 1. To read, the master (microcontroller) first addresses the slave device

after it receives the interrupt. By setting the last bit of the byte containing the slave address to logic 1 the Read mode is entered.

The data bytes that follow on the SDA are the values on the ports.

If the data on the input port changes faster than the master can read, this data may be lost. Transfer of data can be stopped at

any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid.

Figure 9.Read input port register

Power-on reset

When power is applied to VCC, an internal Power-On Reset (POR) holds the PI4IOE5V9673 in a reset condition until VCC

has reached VPOR. At that point, the reset condition is released and the PI4IOE5V9673 registers and I2C-bus/SMBus state

machine will initialize to their default states. Thereafter VCC must be lowered below 0.2 V to reset the device.

Interrupt output (INT)

The PI4IOE5V9673 provides an open-drain interrupt (INT) which can be fed to a corresponding input of the microcontroller.

This gives these chips a kind of master function which can initiate an action elsewhere in the system.

The interrupt disappears when data on the port is changed to the original setting or data is read from or written to the device

which has generated the interrupt.

In the write mode, the interrupt may become deactivated (HIGH) on the rising edge of the write to port pulse. On the falling

edge of the write to port pulse the interrupt is definitely deactivated (HIGH).

The interrupt is reset in the read mode on the rising edge of the read from port pulse.

During the resetting of the interrupt itself, any changes on the I/Os may not generate an interrupt. After the interrupt is reset

any change in I/Os will be detected and transmitted as an INT.

…