34AA04-ESLASHST datasheet(13/36 Pages) MICROCHIP

13 / 36 page

 2014 Microchip Technology Inc.

DS20005271B-page 13

34AA04

8.0

READ OPERATION

Read operations are initiated in the same way as write

operations, with the exception that the R/W bit of the

slave address is set to ‘1’. There are three basic types

of read operations: current address read, random read

and sequential read.

8.1

Current Address Read

The 34AA04 contains an address counter that

maintains the address of the last byte accessed, inter-

nally incremented by ‘1’. Therefore, if the previous

access (either a read or write operation) was to

address n, the next current address read operation

would access data from address n+1. Upon receipt of

the slave address with R/W bit set to ‘1’, the 34AA04

issues an acknowledge and transmits the 8-bit data

value. The master will not acknowledge the transfer,

but does generate a Stop condition and the 34AA04

discontinues transmission (Figure 8-1).

8.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, the array address must first

be set. This is done by sending the array address to the

34AA04 as part of a write operation. Once the array

address is sent, the master generates a Start condition

following the acknowledge. This terminates the write

operation, but not before the internal Address Pointer is

set. The master then issues the control byte again, but

with the R/W bit set to a ‘1’. The 34AA04 then issues

an acknowledge and transmits the 8-bit data word. The

master will not acknowledge the transfer, but does

generate

Stop

condition

and

the

34AA04

discontinues transmission (Figure 8-2).

8.3

Sequential Read

Sequential reads are initiated in the same way as a

random read, with the exception that after the 34AA04

transmits the first data byte, the master issues an

acknowledge, as opposed to a Stop condition in a

random read. This directs the 34AA04 to transmit the

next sequentially addressed 8-bit word (Figure 8-3).

To provide sequential reads, the 34AA04 contains an

internal Address Pointer, which is incremented by one

at the completion of each operation. Sequential reads

are limited to a single bank per operation, so the

Address Pointer allows the entire memory contents of

the current bank to be serially read during one opera-

tion.

8.4

Noise Protection and Brown-Out

The 34AA04 employs a VCC threshold detector circuit

which disables the internal erase/write logic if the VCC

is below 1.35V at nominal conditions.

The SCL and SDA inputs have Schmitt Trigger and

filter circuits which suppress noise spikes to assure

proper device operation, even on a noisy bus.

FIGURE 8-1:

CURRENT ADDRESS READ

Note:

It is recommended to perform a Set Bank

Address command before initiating a

Read command to ensure the desired

bank is selected.

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Data (n)

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