TMS320F241FN datasheet(33/122 Pages) TI1

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TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064D − DECEMBER 1997 − REVISED FEBRUARY 2006

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

interrupt request structure (continued)

Table 10. F243/F241 Interrupt Source Priority and Vectors (Continued)

INTERRUPT

NAME

OVERALL

PRIORITY

CPU

INTERRUPT

AND

VECTOR

ADDRESS

BIT

POSITION IN

PIRQRx AND

PIACKRx

PERIPHERAL

INTERRUPT

VECTOR

(PIV)

MASKABLE?

SOURCE

PERIPHERAL

MODULE

DESCRIPTION

SPIINT

1.7

0005h

SPI

SPI interrupt (low-priority)

RXINT

1.8

0006h

SCI

SCI receiver interrupt

(low-priority mode)

TXINT

INT5

000Ah

1.9

0007h

SCI

SCI transmitter interrupt

(low-priority mode)

CANMBINT

000Ah

1.10

0040h

CAN

CAN mailbox interrupt

(low-priority mode)

CANERINT

1.11

0041h

CAN

CAN error interrupt

(low-priority mode)

ADCINT

1.12

0004h

ADC

ADC interrupt

(low-priority)

XINT1

INT6

000Ch

1.13

0001h

External

Interrupt Logic

External interrupt pins

(low-priority mode)

XINT2

000Ch

1.14

0011h

External

Interrupt Logic

External interrupt pins

(low-priority mode)

Reserved

000Eh

N/A

CPU

Analysis interrupt

TRAP

N/A

0022h

N/A

CPU

TRAP instruction

Phantom

Interrupt

Vector

N/A

0000h

N/A

CPU

Phantom interrupt vector

interrupt acknowledge

When the CPU asserts its interrupt acknowledge, it simultaneously puts a value on the memory interface

program address bus, which corresponds to the CPU interrupt being acknowledged (it does this because it is

fetching the CPU interrupt vector from program memory, each INT has a vector stored in a dedicated program

memory address). This value is shown in Table 10, column 3, CPU Interrupt and Vector Address. The PIE

controller uses the CPU interrupt acknowledge to generate its internal signals to clear the current interrupt

requests.

interrupt vectors

When the CPU receives an interrupt request (INT), it does not know which peripheral event caused the request

(PIRQ). To enable the CPU to distinguish between all of these events, a unique interrupt vector is generated

in response to an active interrupt request getting acknowledged. This vector PIV is loaded into the Peripheral

Interrupt Vector Register (PIVR) in the PIE controller and can then be read by the CPU to generate a branch

to the respective Interrupt Service Routine (ISR).

In effect, there are two vector tables: a CPU vector table and a user-specified peripheral vector table. The CPU’s

vector table, which starts at 0000h, is used to get to the General Interrupt Service Routine (GISR) in response

to a CPU interrupt request (INT). A user-specified peripheral vector table is employed to get to the

Event-Specific Interrupt Service Routine (SISR), corresponding to the event which caused the peripheral

interrupt request (PIRQ). The code in the GISR should read the Peripheral Interrupt Vector Register (PIVR) after

saving any necessary context, and use this value PIV to generate a branch to the SISR.

TMS320F241FN Datasheet(PDF) 33 Page - Texas Instruments

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