MCP19116-ESLASHMJ datasheet(74/246 Pages) MICROCHIP

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MCP19116/7

DS20005479B-page 74

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10.4

USART Synchronous Master

Mode

In Synchronous Master mode, the data is transmitted

in a half-duplex manner (i.e., transmission and recep-

tion do not occur at the same time). When transmitting

data, the reception is inhibited and vice versa. Syn-

chronous mode is entered by setting bit SYNC

(TXSTA<4>).

addition,

enable

bit

SPEN

(RCSTA<7>) is set in order to configure the

GPB6/TX/CK/AN7 and the GPB7/RX/DT/CCD I/O pins

to CK (clock) and DT (data) lines, respectively. The

Master mode indicates that the processor transmits

the master clock on the CK line. The Master mode is

entered by setting bit CSRC (TXSTA<7>).

10.4.1

SYNCHRONOUS MASTER

TRANSMIT MODE

Synchronous Master Transmit mode works similarly to

Asynchronous Transmit mode, see Section 10.3.1

“Asynchronous Transmit Mode”. In Synchronous

Transmit mode, the first data byte is shifted out on the

next available rising edge of the CK line. Data out is

stable relative to the falling edge of the synchronous

clock.

Clearing enable bit TXEN (TXSTA<5>) during a trans-

mission causes the transmission to be aborted and

resets the transmitter. The DT and CK pins revert to

high-impedance. If either bit CREN (RCSTA<4>) or bit

SREN (RCSTA<5>) is set during a transmission, the

transmission is aborted and the DT pin reverts to a

hi-impedance state (for a reception). The CK pin

remains an output if bit CSRC (TXSTA<7>) is set

(internal clock).

The transmitter logic, however, is not reset, although it

is disconnected from the pins. In order to reset the

transmitter, the user has to clear bit TXEN. If bit SREN

is set (to interrupt an on-going transmission and

receive a single word), then after the single word is

received, bit SREN is cleared and the serial port

reverts back to transmitting, since bit TXEN is still set.

The

line

immediately

switches

from

high-impedance Receive mode to transmit and start

driving. To avoid this, it is recommended that the bit

TXEN be cleared.

Steps to follow when setting up a Synchronous Master

Transmission:

Initialize the SPBRG register for the appropriate

baud rate.

Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

If interrupts are desired, set enable bit TXIE.

If 9-bit transmission is desired, set bit TX9.

Enable the transmission by setting bit TXEN.

If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

Start transmission by loading data to the TXREG

If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INT-CON register are set.

FIGURE 10-1: SYNCHRONOUS TRANSMISSION

bit 0

bit 1

bit 7/8

Word 1

Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2Q3 Q4Q1Q2 Q3 Q4Q1 Q2 Q3 Q4

Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4

bit 2

bit 0

bit 1

bit 7

DT pin

CK pin

Write to

TXREG reg

TXIF bit

(Interrupt Flag)

TXEN bit

'1'

Word 2

TRMT bit

Write Word 1

Write Word 2

Note: Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words.

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