MCP19116-ESLASHMJ datasheet(19/246 Pages) MICROCHIP

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 2015-2016 Microchip Technology Inc.

DS20005479B-page 19

MCP19116/7

3.0

FUNCTIONAL DESCRIPTION

3.1

Linear Regulators

The operating input voltage for the MCP19116/7 ranges

from 4.5V to 42V. There are two internal Low Dropout

(LDO) voltage regulators. A 5V LDO is used to power the

internal processor and provide a 5V output for external

usage. A second LDO (AVDD) is a 4V regulator and is

used to power the remaining analog internal circuitry.

AVDD is factory calibrated and is the default ADC refer-

ence voltage. The ADC reference is switchable between

AVDD and VDD. Using an LDO to power the MCP19116/7,

the input voltage is monitored using a resistor divider. The

MCP19116/7 also incorporate brown-out protection.

Refer to Section 14.3 “Brown-out Reset (BOR)” for

details. The PIC core will reset at 2.0V VDD.

3.2

Output Drive Circuitry

The MCP19116/7 integrate two low-side drivers used to

drive the external low-side N-Channel power MOSFETs

for synchronous applications, such as synchronous fly-

back and synchronous Ćuk converters. Both converter

types can be configured for non-synchronous control by

replacing the synchronous FET with a diode. The fly-

back is also capable of quasi-resonant operation. The

MCP19116/7 can also be configured as a Boost or

SEPIC switch-mode power supply (SMPS). In Boost

mode, non-synchronous fixed-frequency or non-syn-

chronous quasi-resonant control can be utilized. This

device can also be used as a SEPIC SMPS in fixed-fre-

quency non-synchronous mode. The low-side drive is

capable of switching the MOSFET at high frequency in

typical SMPS applications. The gate drive (VDR) can be

supplied from 5V to 10V. The drive strength is capable of

up to 1A sink/source with 10V gate drive and down to

0.5A sink/source with 5V gate drive. A programmable

delay is used to set the gate turn-on dead time. This pre-

vents overlap and shoot-through currents that can

decrease the converter efficiency. Each driver has its

own EN input controlled by the microcontroller core.

3.3

Current Sense

The output current is differentially sensed by the

MCP19116/7. In low-current applications, this helps

maintain high system efficiency by minimizing power

dissipation in current-sense resistors. Differential

current sensing also minimizes external ground-shift

errors. The internal differential amplifier has a typical

gain of 10 V/V and is factory trimmed.

3.4

Peak Current Mode

The MCP19116/7 is a peak current mode controlled

device with the current-sensing element in series with

the primary side MOSFET. Programmable leading

edge blanking can be implemented to blank current

spikes resulting from turn on. The blank time is con-

trolled from the ICLEBCON register.

Primary-input current-offset adjust is also available via

user programmability, thus limiting peak primary input

current. This offset adjustment is controlled by the ICO-

ACON register.

3.5

Magnetic Desaturation Detection

An internal comparator module is used to detect power

train magnetic desaturation for quasi-resonant applica-

tions. The comparator output is used as a signal to syn-

chronize the start of the next switching cycle. This

operation differs from the traditional fixed-frequency appli-

cation. The DESAT comparator output can be enabled

and routed into the PWM circuitry or disabled for fixed-fre-

quency applications. During Quasi-Resonant (QR) oper-

ation, the DESAT comparator output is enabled and

combined with a pair of one-shot timers and a flip-flop to

sustain PWM operation. Timer2 (TMR2) must be initial-

ized and set to run at a frequency lower than the minimum

QR operating frequency. When the CDSWDE bit is set in

the DESATCON register, TMR2 serves as a watchdog.

An example of the order of events for a Flyback SMPS in

synchronous QR operation is as follows:

• the primary gate drive (PDRV) goes high

• the output of the DESAT comparator is high

• the primary current increases until IP reaches the

level of the Error Amp and causes PWM compar-

ator output to go low

• the PDRV goes low and the secondary gate drive

(SDRV) goes high (after programmed dead time).

This triggers the first one-shot to send a 200 ns

pulse that resets the flip-flop and TMR2

(WDM_RESET)

• the 200 ns one-shot pulse design is implemented

to mask any spurious transitions at the DESAT

comparator output caused by switching noise

• the SDRV stays high until the secondary winding

completely runs out of energy, at which time the

output capacitance begins to source current back

through the winding and secondary MOSFET

• the DESAT comparator detects this and its output

goes low. This sets the flip-flop and triggers the

second one-shot to send a 33 ns pulse to the con-

trol logic, causing the SDRV to go low and the

PDRV to go high (after programmed dead time)

• the cycle then repeats. If, for any reason, the reset

one-shot does not fire, the WDM_RESET signal

stays low and TMR2 is allowed to run until the

PWM signal kicks off a new cycle

The desaturation comparator module is controlled by

the DESATCON register.

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