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MCP19116-E/MJ Datasheet(PDF) 89 Page - Microchip Technology |
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MCP19116-E/MJ Datasheet(HTML) 89 Page - Microchip Technology |
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89 / 246 page  TABLE 11-5: MCP19116/7 SPECIAL REGISTERS SUMMARY BANK 3 Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Values on all other resets (1) Bank 3 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu 181h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 182h PCL Program Counter's (PC) Least Significant byte 0000 0000 0000 0000 183h STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 000q quuu 184h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 185h IOCA IOCA7 IOCA6 IOCA5 — IOCA3 IOCA2 IOCA1 IOCA0 000- 0000 0000 0000 186h IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — IOCB1 IOCB0 0000 --00 0000 --00 187h ANSELA — — — — ANSA3 ANSA2 ANSA1 ANSA0 ---- 1111 ---- 1111 188h ANSELB — ANSB6 ANSB5 ANSB4 — —ANSB1 — -111 --1- -111 --1- 189h — Unimplemented — — 18Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 18Bh INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF (2) 0000 000x 0000 000u 18Ch PORTICD (3) In-Circuit Debug Port Register xxx --xx uuuu --uu 18Dh TRISICD (3) In-Circuit Debug TRIS Register 1111 0011 1111 0011 18Eh ICKBUG (3) In-Circuit Debug Register 0000 0000 000u uuuu 18Fh BIGBUG (3) In-Circuit Debug Breakpoint Register 0000 0000 uuuu uuuu 190h PMCON1 — CALSEL — — —WREN WR RD -0-- -000 -0-- -000 191h PMCON2 Program Memory Control Register 2 (not a physical register) ---- ---- ---- ---- 192h PMADRL PMADRL7 PMADRL6 PMADRL5 PMADRL4 PMADRL3 PMADRL2 PMADRL1 PMADRL0 0000 0000 0000 0000 193h PMADRH — — — — PMADRH3 PMADRH2 PMADRH1 PMADRH0 ---- -000 ---- -000 194h PMDATL PMDATL7 PMDATL6 PMDATL5 PMDATL4 PMDATL3 PMDATL2 PMDATL1 PMDATL0 0000 0000 0000 0000 195h PMDATH — — PMDATH5 PMDATH4 PMDATH3 PMDATH2 PMDATH1 PMDATH0 --00 0000 --00 0000 196h DSTCAL — — — DSTCAL4 DSTCAL3 DSTCAL2 DSTCAL1 DSTCAL0 ---x xxxx ---u uuuu 197h RFBTCAL — — RFBCAL5 RFBCAL4 RFBCAL3 RFBCAL2 RFBCAL1 RFBCAL0 --xx xxxx --uu uuuu 198h OSCCAL — FCALT6 FCALT5 FCALT4 FCALT3 FCALT2 FCALT1 FCALT0 -xxx xxxx -uuu uuuu 199h DCSCAL — DCSCAL6 DCSCAL5 DCSCAL4 DCSCAL3 DCSCAL2 DCSCAL1 DCSCAL0 -xxx xxxx -uuu uuuu 19Ah TTACAL — — — — TTA3 TTA2 TTA1 TTA0 ---- xxxx ---- uuuu 19Bh BGRCAL — — — BGRT4 BGRT3 BGRT2 BGRT1 BGRT0 ---x xxxx ---u uuuu 19Ch EAOFFCAL — — — EAOFFCAL4 EAOFFCAL3 EAOFFCAL2 EAOFFCAL1 EAOFFCAL0 ---x xxxx ---u uuuu 19Dh AVDDCAL — — — — AVDDCAL3 AVDDCAL2 AVDDCAL1 AVDDCAL0 ---- xxxx ---- uuuu 19Eh A2GCAL — — — — A2GCAL3 A2GCAL2 A2GCAL1 A2GCAL0 ---- xxxx ---- uuuu 19Fh OVRSPCAL — — — OVRSPCAL4 OVRSPCAL3 OVRSPCAL2 OVRSPCAL1 OVRSPCAL0 ---x xxxx ---u uuuu Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: MCLR and WDT reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will be set again if the mismatch exists. 3: Only accessible when DBGEN = 0 and ICKBUG<INBUG> = 1. |
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