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MCP19116-E/MJ Datasheet(PDF) 78 Page - Microchip Technology

Part # MCP19116-E/MJ
Description  Digitally Enhanced Power Analog Synchronous Low-Side PWM Controller with Improved 8k Word Core
PDF  246 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP19116-E/MJ Datasheet(HTML) 78 Page - Microchip Technology

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MCP19116/7
DS20005479B-page 78
 2015-2016 Microchip Technology Inc.
REGISTER 10-1: RCSTA – RECEIVE STATUS AND CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-x
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SPEN (1): Serial Port Enable bit
1 = Serial port enabled - configures GPB7/RX/DT/CCD and GPB6/TX/CK/AN7 pins as serial port pins
0 = Serial port disabled - module and its state machines held in Reset
bit 6
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit
Asynchronous mode:
Unused in this mode - value ignored
Synchronous mode - master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave:
Unused in this mode - value ignored
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
RX9 = 1:
1
=
Enables address detection - enable interrupt and load of the receive buffer when the ninth bit in
the receive buffer is set
0
=
Disables address detection - all bytes are received, and ninth bit can be used as parity bit
RX9 = 0:
Unused in this mode
bit 2
FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1
OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0
RX9D: 9th bit of received data (can be parity bit)
Note 1:
The USART module automatically changes the pin from tri-state to drive as needed. Configure
TRISC<5> = 1 and TRISC<4> = 1.



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