EMC1428 datasheet(30/53 Pages) MICROCHIP

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1°C Multiple Temperature Sensor with HW Thermal Shutdown & Hottest of Thermal Zones

Data Sheet

DS20005275A-page 30

 2014 Microchip Technology Inc.

5.3

Status Register

The Status Register reports general error conditions. To identify specific channels, refer to Section 5.9,

Section 5.18, Section 5.19, and Section 5.20. The individual Status Register bits (except HOTTEST)

are cleared when the appropriate High Limit, Low Limit, or THERM Limit register has been read or

cleared.

Bit 7 - BUSY - This bit indicates that the ADC is currently converting. This bit does not cause the

ALERT pin to be asserted.

Bit 6 - HOTTEST - This bit is set if the REM_HOT bit (see Section 5.23) is set and the hottest channel

changes. This bit is cleared when the register is read.

Bit 4 - HIGH - This bit is set when any of the temperature channels meets or exceeds its programmed

high limit. See the High Limit Status Register for specific channel information (Section 5.18). When set,

this bit will assert the ALERT pin.

Bit 3 - LOW - This bit is set when any of the temperature channels drops below its programmed low

limit. See the Low Limit Status Register for specific channel information (Section 5.19). When set, this

bit will assert the ALERT pin.

Bit 2 - FAULT - This bit is asserted when a diode fault is detected on any of the external diode

channels. See the External Diode Fault Register for specific channel information (Section 5.9). When

set, this bit will assert the ALERT pin.

Bit 1 - SW_SYS - This bit is set when any of the external diode channels meet or exceed the respected

THERM Limits. See the Therm Status Register for specific channel information (Section 5.20)

Bit 0 - HWSD - This bit is set when the External Diode 1 Temperature meets or exceeds the Hardware

Critical / Thermal Shutdown Limit. When set, this bit will assert the SYS_SHDN pin. This bit is cleared

when read if the SYS_SHDN pin has been released.

5.4

Configuration Register

The Configuration Register controls the basic operation of the device. This register is fully accessible

at either address.

Table 5.4 Status Register

ADDR

R/W

DEFAULT

02h

Status

BUSY

HOT

TEST

HIGH

LOW

FAULT

SW_

SYS

HWSD

00h

Table 5.5 Configuration Register

ADDR

R/W

DEFAULT

03h

R/W

Config

MASK_

ALL

ALERT/

COMP

DAVG_

DIS

00h

09h

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