ST72561 datasheet(188/262 Pages) STMICROELECTRONICS

188 / 262 page

ST72561

188/262

beCAN CONTROLLER (Cont’d)

– The FIFO interrupt can be generated by the fol-

lowing events:

– Reception of a new message, FMP bits in the

CRFR0 register incremented.

– FIFO0 full condition, FULL bit in the CRFR0

– FIFO0 overrun condition, FOVR bit in the

CRFR0 register set.

– The transmit, error and status change inter-

rupt can be generated by the following events:

– Transmit mailbox 0 becomes empty, RQCP0

bit in the CTSR register set.

– Transmit mailbox 1 becomes empty, RQCP1

bit in the CTSR register set.

– Error condition, for more details on error con-

ditions please refer to the CAN Error Status

– Wake-up condition, SOF monitored on the

CAN Rx signal.

10.9.6 Register Access Protection

Erroneous access to certain configuration regis-

ters can cause the hardware to temporarily disturb

the whole CAN network. Therefore the following

registers can be modified by software only while

the hardware is in initialization mode:

CBTR0, CBTR1, CFCR0, CFCR1, CFMR and

CDGR registers.

Although the transmission of incorrect data will not

cause problems at the CAN network level, it can

severely disturb the application. A transmit mail-

box can be only modified by software while it is in

empty state, refer to Figure 100.Transmit Mailbox

States

The filters must be deactivated before their value

can be modified by software. The modification of

the filter configuration (scale or mode) can be

done by software only in initialization mode.

ST72561 Datasheet(PDF) 188 Page - STMicroelectronics