ST72561 datasheet(190/262 Pages) STMICROELECTRONICS

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ST72561

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beCAN CONTROLLER (Cont’d)

Workaround

To implement the workaround, use the following

sequence to release the CAN receive FIFO.

This sequence replaces any occurrence of

CRFR |= B_RFOM;

Figure 110. Workaround 1

Explanation of Workaround 1

First, we need to make sure no interrupt can occur

between the test and the release of the FIFO to

avoid any added delay.

The workaround checks if the first 2 FIFO levels

are already full (FMP = 2) as the problem happens

only in this case.

If FMP

≠2 we release the FIFO immediately, if

FMP=2, we monitor the reception status of the

cell.

The reception status is available in the CMSR reg-

ister bit 5 (REC bit). Note: The REC bit was called

RX in olders versions of the datasheet.

– If the cell is not receiving, then REC bit in CMSR

is at 0, the software can release the FIFO imme-

diately: there is no risk.

– If the cell is receiving, it is important to make sure

the release of the mailbox will not happen at the

time when the received message is loaded into

the FIFO.

We could simply wait for the end of the reception,

but this could take a long time (200µs for a 100-bit

frame at 500kHz), so we also monitor the Rx pin of

the microcontroller to minimize the time the appli-

cation may wait in the while loop.

We know the critical window is located at the end

of the frame, 6+ CAN bit times after the acknowl-

edge bit (exactly six full bit times plus the time from

the beginning of the bit to the sample point). Those

bits represent the acknowledge delimiter + the end

of frame slot.

We know also that those 6+ bits are in recessive

state on the bus, therefore if the CAN Rx pin of the

device is at ‘0’, (reflecting a CAN dominant state

on the bus), this is early enough to be sure we can

release the FIFO before the critical time slot.

Therefore, if the device hardware pin Rx is at 0

and there is a reception on going, its message will

be transferred to the FIFO only 6+ CAN bit times

later at the earliest (if the dominant bit is the ac-

knowledge) or later if the dominant bit is part of the

message.

Compiled with Cosmic C compiler, the workaround

generates the following assembly lines:

if ((CRFR & 0x03) == 0x02)

while

(( CMSR & 0x20) && ( CDGR & 0x08) )

{ };

CRFR |= B_RFOM;

Cycles

if ((CRFR & 0x03) == 0x02)

a, CRFR

and

a,#3

a,#2

jrne

_RELEASE

test: 10 cycles

while

(( CMSR & 0x20) && ( CDGR & 0x08) )

{ };

_WHILELOOP:

btjf

CMSR,#5,_RELEASE

btjt

CDGR,#3,_WHILELOOP

loop: 10 cycles

CRFR |= B_RFOM;

_RELEASE:

bset

CRFR,#5

release: 5 cycles

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