ST72561 datasheet(192/262 Pages) STMICROELECTRONICS

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ST72561

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beCAN CONTROLLER (Cont’d)

Side-effect of Workround 1

Because the while loop lasts 10 CPU cycles, at

high baud rate, it is possible to miss a dominant

state on the bus if it lasts just one CAN bit time and

the bus speed is high enough (see Table 28)

Table 28. While Loop Timing

If this happens, we will continue waiting in the

while loop instead of releasing the FIFO immedi-

ately. The workaround is still valid because we will

not release the FIFO during the critical period. But

the application may lose additional time waiting in

the while loop as we are no longer able to guaran-

tee a maximum of 6 CAN bit times spent in the

workaround.

In this particular case the time the application can

spend in the workaround may increase up to a full

CAN frame, depending of the frame contents. This

case is very rare but happens when a specific se-

quence is present on in the CAN frame.

The example in Figure 113 shows reception at

maximum CAN baud rate: in this case TCAN is 8/

Fcpu and the sampling time is 10/Fcpu.

If the application is using the maximum baud rate

and the possible delay caused by the workaround

is not acceptable, there is another workaround

which reduces the Rx pin sampling time.

Workaround 2 (see Figure 114) first tests that

FMP=2 and the CAN cell is receiving, if not the

FIFO can be released immediately. If yes, the pro-

gram goes through a sequence of test instructions

on the RX pin that last longer than the time be-

tween the acknowledge dominant bit and the criti-

cal time slot. If the Rx pin is in recessive state for

more than 8 CAN bit times, it means we are now

after the acknowledge and the critical slot. If a

dominant bit is read on the bus, we can release the

FIFO immediately. This workaround has to be writ-

ten in assembly language to avoid the compiler

optimizing the test sequence.

The implementation shown here is for the CAN

bus maximum speed (1MBd @ 8MHz CPU clock).

Figure 113. Reception at maximum CAN baudrate

fCPU

Software

timing:

While loop

Minimum baud rate for

possible missed

dominant bit

8 MHz

1.25 µs

800 kBaud

4 MHz

2.5 µs

400 kBaud

fCPU

10/fCPU

fCPU/10

Sampling of Rx pin

CAN Bus signal

D R RR R D R RR R

R R R R

D R RR R D R R R R D

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