ST72561 datasheet(191/262 Pages) STMICROELECTRONICS

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ST72561

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beCAN CONTROLLER (Cont’d)

In the worst case configuration, if the CAN cell

speed is set to the maximum baud rate, one bit

time is 8 CPU cycle. In this case the minimum time

between the end of the acknowledge and the criti-

cal period is 52 CPU cycles (48 for the 6 bit times

+ 4 for the (PROP SEG + TSeg 1). According to the

previous code timing, we need less than 15 cycles

from the time we see the dominant state to the

time we perform the FIFO release (one full loop +

the actual release) therefore the application will

never release the FIFO at the critical time when

this workaround is implemented.

Timing analysis

- Time spent in the workaround

Inside a CAN frame, the longest period that the Rx

pin stays in recessive state is 5 bits. At the end of

the frame, the time between the acknowledge

dominant bit and the end of reception (signaled by

REC bit status) is 8TCANbit, therefore the maxi-

mum

time

spent

the

workaround

is:

8TCANbit+Tloop+Ttest+Trelease in this case or

8TCANbit+25TCPU.

At low speed, this time could represent a long de-

lay for the application, therefore it makes sense to

evaluate how frequently this delay occurs.

In order to reach the critical FMP=2, the CAN node

needs to receive 2 messages without servicing

them. Then in order to reach the critical window,

the cell has to receive a third one and the applica-

tion has to release the mailbox at the same time, at

the end of the reception.

In the application, messages are not processed

only if either the interrupt are disabled or higher

level interrupts are being serviced.

Therefore if:

TIT higher level + TIT disable + TIT CAN < 2 x T CAN frame

the application will never wait in the workaround

TIT higher level: This the sum of the duration of all the

interrupts with a level strictly higher than the CAN

interrupt level

TIT disable: This is the longest time the application

disables the CAN interrupt (or all interrupts)

TIT CAN: This is the maximum duration between

the beginning of the CAN interrupt and the actual

location of the workaround

TCAN frame: This is minimum CAN frame duration

Figure 111. Critical Window Timing Diagram

Figure 112. Reception of a Sequence of Frames

A release is not

allowed at this time

Critical window: the received

message is placed in the FIFO

CAN Frame

Acknowledge: last

dominant bit in the frame

Time to test RX pin and to

release the FIFO 4.5 µs@4MHz Time between the end of the

acknowledge and the critical windows

- 6 full CAN bit times+ time to the sample point

approx. 13µs @ 500kBd

TCAN frame 1TCAN frame 2TCAN frame 3

FMP

BUS

CPU

TIT disable

TIT higher level

TIT CAN

ST72561 Datasheet(PDF) 191 Page - STMicroelectronics

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