USB SS

PHY

USB HS/FS

PHY

USB 3.0

Device

Controller

ARM

Cortex M3

ROM

RAM

64 kB

Watchdog

Timer

Timer

SCI

(UART)

GPIO

PWM

SATA II

PHY

SATA

AHCI

SPI

GRSTz

VDD3.3

VDD1.1

Power

and

Reset

Distribution

Clock

Generation

XI

X0

JTAG

TCK

TMS

TDO

TDI

TRST

Data Path

RAM

80 kB

TUSB9261-Q1

SLLSEE2A – JANUARY 2014 – REVISED JANUARY 2014

www.ti.com

DESCRIPTION

The TUSB9261-Q1 is an ARM cortex M3 microcontroller based Universal Serial Bus (USB) 3.0 to Serial ATA

(SATA) bridge. It provides the necessary hardware and firmware to implement a USB Attached SCSI Protocol

(UASP) compliant mass storage device suitable for bridging SATA compatible hard disk drives (HDD) and solid

state disk drives (SSD) to a USB 3.0 bus. The firmware also implements the mass storage class bulk-only

transport (BOT) for bridging optical drives and other compatible SATA devices to the USB bus. In addition to

UASP and BOT support,a USB human interface device (HID) interfaces is supported for control of the general

purpose input/ouput (GPIO). The SATA interface supports gen1 (1.5-Gbps) and gen2 (3.0-Gbps) for cable

lengths up to 2 meters.

The device is available in a 64-pin HTQFP package and is designed for operation over the industrial temperature

range of -40°C to 85°C.

Figure 1. TUSB9261-Q1 Block Diagram

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

2

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Product Folder Links :TUSB9261-Q1