TUSB9261-Q1

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SLLSEE2A – JANUARY 2014 – REVISED JANUARY 2014

Table 4. USB Interface Signals

TERMINAL

I/O

DESCRIPTION

PIN

NAME

NO.

USB_SSTXP

43

O

SuperSpeed USB transmitter differential pair (positive)

USB_SSTXM

42

O

SuperSpeed USB transmitter differential pair (negative)

USB_SSRXP

46

I

SuperSpeed USB receiver differential pair (positive)

USB_SSRXM

45

I

SuperSpeed USB receiver differential pair (negative)

USB_DP

36

I/O

USB High-speed differential transceiver (positive)

USB_DM

35

I/O

USB High-speed differential transceiver (negative)

USB Upstream port power monitor. The USB_VBUS input is a 1.2V I/O cell and requires a voltage

divider to prevent damage to the input. The signal USB_VBUS must be connected to VBUS

USB_VBUS

50

I

through a 90.9 k

Ω ±1% resistor, and to signal ground through a 10 kΩ ±1% resistor. This allows

the input to detect VBUS present from a minimum of 4V and sustain a maximum VBUS voltage up

to 10V (applied to the voltage divider).

USB_R1

38

O

Precision resistor reference. A 10-k

Ω ±1% resistor should be connected between R1 and R1RTN.

USB_R1RTN

39

I

Precision resistor reference return

Table 5. Serial Peripheral Interface (SPI) Signals

TERMINAL

I/O

DESCRIPTION

PIN

NAME

NO.

O

SPI_SCLK

17

SPI clock

PU

O

SPI_DATA_OUT

18

SPI master data out

PU

I

SPI_DATA_IN

20

SPI master data in

PU

O

SPI_CS0

21

Primary SPI chip select for Flash RAM

PU

SPI_CS2/

I/O

SPI chip select for additional peripherals. When not used for SPI chip select this pin may be used

23

PU

as general purpose I/O. SeeTable 8 for firmware configuration defaults.

GPIO11

SPI_CS1/

I/O

SPI chip select for additional peripherals. When not used for SPI chip select this pin may be used

22

PU

as general purpose I/O. SeeTable 8 for firmware configuration defaults.

GPIO10

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