TNETV6421INZDU4 datasheet(8/222 Pages) TI1

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2.2 C64x+ Megamodule

2.2.1

C64x+ Memory Architecture

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346D – JANUARY 2007 – REVISED JUNE 2008

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Table 2-1. Characteristics of the C6421 Processor (continued)

HARDWARE FEATURES

C6421

16 x 16 mm, 0.8 mm pitch

361-Pin BGA (ZWT)

BGA Package(s)

23 x 23 mm, 1.0 mm pitch

376-Pin BGA (ZDU)

Process Technology

µm

0.09

µm

Product Preview (PP), Advance Information (AI),

Product Status(2)

or Production Data (PD)

(2)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

The C64x+ Megamodule implements a two-level internal cache-based memory architecture with external

memory support. The Level 1 Program memory/cache (L1P) consists of 16 KB memory space that can be

configured as mapped memory or direct mapped cache. The Level 1 Data memory/cache (L1D) consists

of 48 KB memory space which can be configured as mapped memory or 2-way set associated cache. The

Level 2 memory/cache (L2) consists of a 64 KB memory space that is shared between program and data

space. L2 memory can be configured as mapped memory, cache, or a combination of both.

Table 2-2 shows a memory map of the C64x+ CPU cache register for the device.

Figure 2-1, shows a diagram of the C64x+ Cache Memory Architecture.

Table 2-2. C64x+ Cache Registers

HEX ADDRESS RANGE

DESCRIPTION

0x0184 0000

L2CFG

L2 Cache configuration register

L1P Size Cache configuration register (see Section 2.2.1.1, L1P

0x0184 0020

L1PCFG

Configuration Register (L1PCFG) Description)

0x0184 0024

L1PCC

L1P Freeze Mode Cache configuration register

L1D Size Cache configuration register (see Section 2.2.1.2, L1D

0x0184 0040

L1DCFG

Configuration Register (L1DCFG) Description)

0x0184 0044

L1DCC

L1D Freeze Mode Cache configuration register

0x0184 0048 - 0x0184 0FFC

Reserved

0x0184 1000

EDMAWEIGHT

L2 EDMA access control register

0x0184 1004 - 0x0184 1FFC

Reserved

0x0184 2000

L2ALLOC0

L2 allocation register 0

0x0184 2004

L2ALLOC1

L2 allocation register 1

0x0184 2008

L2ALLOC2

L2 allocation register 2

0x0184 200C

L2ALLOC3

L2 allocation register 3

0x0184 2010 - 0x0184 3FFF

Reserved

0x0184 4000

L2WBAR

L2 writeback base address register

0x0184 4004

L2WWC

L2 writeback word count register

0x0184 4010

L2WIBAR

L2 writeback invalidate base address register

0x0184 4014

L2WIWC

L2 writeback invalidate word count register

0x0184 4018

L2IBAR

L2 invalidate base address register

0x0184 401C

L2IWC

L2 invalidate word count register

0x0184 4020

L1PIBAR

L1P invalidate base address register

0x0184 4024

L1PIWC

L1P invalidate word count register

0x0184 4030

L1DWIBAR

L1D writeback invalidate base address register

0x0184 4034

L1DWIWC

L1D writeback invalidate word count register

0x0184 4038

Reserved

Device Overview

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