TNETV6421INZDU4 datasheet(12/222 Pages) TI1

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2.2.1.2 L1D Configuration Register (L1DCFG) Description

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346D – JANUARY 2007 – REVISED JUNE 2008

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RESERVED

R-0000 0000 0000 0000

RESERVED

L1PMODE

R- 0000 0000 0000 0

R/W-111 (7h)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.

Figure 2-2. L1PCFG Register

Table 2-3. L1PCFG Register Bit Descriptions

Bit

Field Name

Description

31:3

RESERVED

Reserved. Read-only, writes have no effect.

L1PMODE select.

000 [0h] = L1P Cache Disabled

001 [1h] = 4 KB

2:0

L1PMODE

010 [2h] = 8 KB

011 [3h] = 16KB

100 [4h] – 111 [7h] = Reserved. Do Not Use.(1)

(1)

For proper C6421 device operation, only settings 000 [0h] through 011 [3h] are valid. To intialize L1P RAM/Cache to a valid cache

setting, the user must follow the sequence outlined in Section 3.8, Device Initialization Sequence After Reset. For more details, see the

TMS320C6424/21 Digital Signal Processor (DSP) Silicon Errata [Silicon Revisions 1.1 and 1.0] (literature number SPRZ252).

The L1D Configuration Register (L1DCFG) controls/defines the size of the L1D cache. The format and bit

field descriptions of the L1DCFG register for the C6421 are shown in Figure 2-3 and Table 2-4,

respectively.

RESERVED

R-0000 0000 0000 0000

RESERVED

L1DMODE

R- 0000 0000 0000 0

R/W-111 (7h)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset.

Figure 2-3. L1DCFG Register

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