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TMS320VC5421 Datasheet(PDF) 19 Page - Texas Instruments |
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TMS320VC5421 Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 104 page ![]() Introduction 19 December 1999 − Revised October 2008 SPRS098D 2.4 Signal Descriptions Table 2−3 lists each signal, function, and operating mode(s) grouped by function. See pin assignments section for exact pin locations based on package type. Table 2−3. Signal Descriptions PIN NAME TYPE† DESCRIPTION DATA SIGNALS PPA18 (MSB) PPA17 PPA16 PPA15 PPA14 PPA13 PPA12 PPA11 PPA10 PPA9 PPA8 PPA7 PPA6 PPA5 PPA4‡§ PPA3 PPA2 PPA1 PPA0 (LSB) I/O/Z Parallel port address bus. The DSP can access the external memory locations by way of the external memory interface using PPA[18:0] in external memory interface (EMIF) mode when the XIO pin is logic high. PPA18 is a secondary output function of the SELA/B pin. The PPA[17:0] pins are also multiplexed with the HPI interface. In HPI mode (XIO pin is low), the external address pins PPA[17:0] are used by a host processor for access to the memory map by way of the on-chip HPI. Refer to the Host-Port Interface (HPI) Signals section of this table for details on the secondary functions of these pins. These pins are placed into the high-impedance state when OFF is low. † I = Input, O = Output, S = Supply, Z = High Impedance ‡ This pin has an internal pullup resistor. § These pins are Schmitt triggered inputs. ¶ This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A . # This pin is used by Texas Instruments for device testing and should be left unconnected. || This pin has an internal pulldown resistor. kAlthough this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs, a buffer is recommended to ensure the VIL and VIH specifications are met. |
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