TMS320VC5421 datasheet(41/104 Pages) TI1

41 / 104 page

Functional Overview

December 1999 − Revised October 2008

SPRS098D

Table 3−9. Transmit Channel Enable Registers for Partitions A to H

Bit

Name

Function

15−0

XCERyz(15:0)

Transmit Channel Enable Register

XCERyz n =0

Disables transmit of nth channel in partition y.

XCERyz n =1

Enables transmit of nth channel in partition y.

Note:

y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2; n = bit 15−0

The clock stop mode (CLKSTP) in the McBSP provides compatibility with the serial port interface (SPI)

protocol. Clock stop mode works with only single-phase frames and one word per frame. The word sizes

supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP

is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or

as a slave.

The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum McBSP multichannel

operating frequency on the 5421 is 9 MBps. Nonmultichannel operation is limited to 38 MBps.

3.7.1 Emulation Considerations

The McBSP can continue operation even when the DSP CPU is halted due to debugger breakpoints or other

emulation events.

TMS320VC5421 Datasheet(PDF) 41 Page - Texas Instruments