TMS320VC5421 datasheet(40/104 Pages) TI1

40 / 104 page

Functional Overview

December 1999 − Revised October 2008

SPRS098D

Reserved

RMCME

RPBBLK

RPABLK

RCBLK

RMCM

R,+0

RW,+0

R,+0

RW,+0

Note:

R = Read, W = Write, +0 = Value at reset; x = McBSP 0,1, or 2

Figure 3−10. Multichannel Control Register 1x (MCR1x)

•

In the second mode, with RMCME = 1 and XMCME = 1, the McBSPs have 128 channel selection

capability. Twelve new registers (RCERCx−RCERHx and XCERCx−XCERHx) are used to enable the

128 channel selection. The subaddresses of the new registers are shown in Table 3−21. These new

registers, functionally equivalent to the RCERA0−RCERB1 and XCERA0−XCERB1 registers in the 5420,

are used to enable/disable the transmit and receive of additional channel partitions (C,D,E,F,G, and H)

in the 128 channel stream. For example, XCERH1 is the transmit enable for channel partition H (channels

112 to 127) of MCBSP1 for each DSP subsystem. See Figure 3−11, Table 3−8, Figure 3−12, and

Table 3−9 for bit layout and function of the receive and transmit registers .

RCERyz15

RCERyz14

RCERyz13

RCERyz12

RCERyz11

RCERyz10

RCERyz9

RCERyz8

RW,+0

RCERyz7

RCERyz6

RCERyz5

RCERy4

RCERyz3

RCERyz2

RCERyz1

RCERyz0

RW,+0

Note:

R = Read, W = Write, +0 = Value at reset; y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2

Figure 3−11. Receive Channel Enable Registers Bit Layout for Partitions A to H

Table 3−8. Receive Channel Enable Registers for Partitions A to H

Bit

Name

Function

15−0

RCERyz(15:0)

Receive Channel Enable Register

RCERyz n =0

Disables reception of nth channel in partition y.

RCERyz n =1

Enables reception of nth channel in partition y.

Note:

y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2; n = bit 15−0

XCERyz15

XCERyz14

XCERyz13

XCERyz12

XCERyz11

XCERyz10

XCERyz9

XCERyz8

RW,+0

XCERyz7

XCERyz6

XCERyz5

XCERy4

XCERyz3

XCERyz2

XCERyz1

XCERyz0

RW,+0

Note:

R = Read, W = Write, +0 = Value at reset; y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2

Figure 3−12. Transmit Channel Enable Registers Bit Layout for Partitions A to H

TMS320VC5421 Datasheet(PDF) 40 Page - Texas Instruments

TMS320VC5421 Datasheet(HTML) 40 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL