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TMS320VC5421 Datasheet(PDF) 48 Page - Texas Instruments |
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TMS320VC5421 Datasheet(HTML) 48 Page - Texas Instruments |
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48 / 104 page  Functional Overview 48 December 1999 − Revised October 2008 SPRS098D 3.8.7 Chip Subsystem ID Register The chip subsystem ID Register (CSIDR) is a read-only memory-mapped register located at 3Eh within each DSP subsystem. This register contains three elements for electrically readable device identification. The ChipID bits identify the type of 54x device (21h for 5421). The ChipRev bits contain the revision number of the device. Lastly, the SubSysID contains a unique subsystem identifier. 15 14 13 12 11 10 987 6 5 43210 Chip ID Chip Rev SubSysID Figure 3−18. Chip Subsystem ID Register Table 3−13. Chip Subsystem ID Register Bit Functions BIT NO. BIT FIELD NAME FUNCTION 15−8 Chip ID 54x device type. Contains 21h for 5421. 15−8 Chip ID 54x device type. Contains 21h for 5421. 7−4 Chip Rev Revision number of device (i.e., 0h for revision 0). 3−0 SubSysID Identifier for DSP subsystem: A = 0h, B = 1h. 3−0 SubSysID Identifier for DSP subsystem: A = 0h, B = 1h. 3.9 General-Purpose I/O In addition to the A_XF and B_XF pins, the 5421 has eight general-purpose I/O pins. These pins are: A_GPIO0, A_GPIO1, A_GPIO2, A_GPIO3 B_GPIO0, B_GPIO1, B_GPIO2, B_GPIO3 Four general-purpose I/O pins are available to each core. Each GPIO pin can be individually selected as either an input or an output. Additionally, the timer output is selectable on GPIO pin 3. At core reset, all GPIO pins are configured as inputs. GPIO data and control bits are accessible through a memory-mapped register at 3Ch with the format shown in Figure 3−19. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOUT Reserved GPIO DIR3 GPIO DIR2 GPIO DIR1 GPIO DIR0 ROM EN CORE SEL XIO GRANT XIO REQ GPIO DAT3 GPIO DAT2 GPIO DAT1 GPIO DAT0 R/W+0 R/W+0 R/W+0 R/W+0 R/W+0 R/W† R R+0 R/W+0 R/W+0 R/W+0 R/W+0 R/W+0 † 1 denotes XIO = 1, 0 denotes XIO = 0 Note: R = Read, W = Write, +0 = Value at reset Figure 3−19. General-Purpose I/O Control Register |
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