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L6718 Datasheet(PDF) 54 Page - STMicroelectronics |
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L6718 Datasheet(HTML) 54 Page - STMicroelectronics |
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54 / 71 page ![]() Output voltage positioning L6718 54/71 DocID023399 Rev 3 Equation 9 where ΔVosc is the PWM ramp and kV the gain for the voltage loop (see Figure 12). During a DVID transition, the REF pin moves according to the command issued (SetVIDFast, SetVIDSlow); the current requested to charge/discharge the RREF/CREF network is mirrored and added to the droop current compensating for over/undershoot on the regulated voltage. If Jmode is enabled by CONFIG1 pinstrapping the SREF/JEN is set as the single-phase rail enable. Figure 12. DVID optimization circuit C REF C F 1 ΔV OSC k V V IN ⋅ ---------------------- – ⎝⎠ ⎛⎞ ⋅ = R REF R F C F ⋅ C REF ---------------------- = Ref REF RREF CREF Ref COMP RF CF RFB ZF(s) ZFB(s) VID to Vout... RGND AM12886v1 |
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