DFE252012C datasheet(6/17 Pages) MGCHIP

6 / 17 page

Confidential

Datasheet Version 1.1

Mar. 2015. Revision 1.1

MagnaChip Semiconductor Ltd.

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

2C interface (Note 1)

VOL

Output Data Logic Low Voltage

IPULLUP=4mA

0.17

ILEAK

Input Leakage on SDA/SCL

-10

tEN_I2C

Minimum time Between EN high

and I2C Enabled

0.5

fSCL

SCL Clock Frequency

400

kHz

Bus Free Time Between stop and

Start condition

1.3

tHD:STA Hold Time after(Repeated)

START condition

After this Period, the First

Clock is generated

0.6

tSU:STA

Repeated Start condition setup

time

0.6

tSU:STO

Stop Condition Setup Time

0.6

tHD:DAT

Data Hold Time

300

tSU:DAT

Data Setup Time

100

Low Period of SCL Clock

1.3

High Period of SCL Clock

0.6

Clock/Data Fall Time

300

Clock/Data Rise Time

300

CCDMAX

Clock/data Maximum

Capacitance

400

Note1) Guaranteed by design; not test in production

Definition of timing for F/S-mode devices on the I

2C bus

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