Confidential

Datasheet Version 1.1

Mar. 2015. Revision 1.1

MagnaChip Semiconductor Ltd.

14

S

T

R

T

S

T

O

P

M

S

B

L

S

B

L

S

B

M

S

B

M

S

B

L

S

B

7bit DEVICE

ADDRESS

W

/

R

A

C

K

A

C

K

A

C

K

8bit ADDRESS OF

REGISTER

DATA

W

R

T

SCL

SDA

Figure 25 Writing to a single register

WRITING TO MULTIPLE REGISTERS WITH INCREMENTAL ADDRESSING

It would be unpractical to send several times the device address and the address of the register when

writing to multiple registers. MAP7102 supports writing to multiple registers with incremental addressing.

When data is written to a register, the address register is automatically incremented. So the next data can

be sent without sending the device address and the register address again.

7bit DEVICE

ADDRESS

8bit ADDRESS OF

REGISTER i

DATA i

DATA i+1

DATA i+n-1

DATA i+n

M

S

B

L

S

B

L

S

B

M

S

B

M

S

B

L

S

B

W

/

R

A

C

K

A

C

K

A

C

K

L

S

B

M

S

B

M

S

B

L

S

B

A

C

K

A

C

K

A

C

K

W

R

T

M

S

B

L

S

B

SCL

SDA

Figure 26 Writing to multiple registers

READING FROM A SINGLE REGISTER

The reading operation starts with a START bit followed by the 7bit device address of MAP7102. The 8-th bit

is the W/R bit, which is 0 in this case. MAP7102 confirms the receiving of the address + W/R bit by an

acknowledge pulse. The address of the register which should be read is sent afterwards and confirmed

again by an acknowledge pulse of MAP7102 again. Then the master generates a START bit again and

sends the device address followed by the W/R bit, which is 1 now. MAP7102 confirms the receiving of the

address+ W/R bit by an acknowledge pulse and starts to send the data to the master. No acknowledge

pulse from the master is required after receiving the data. Then the master generates a STOP bit to

terminate the communication.

7bit DEVICE

ADDRESS

8bit ADDRESS OF

REGISTER

DATA

7bit DEVICE

ADDRESS

S

T

R

T

M

S

B

L

S

B

L

S

B

M

S

B

M

S

B

W

/

R

A

C

K

A

C

K

L

S

B

A

C

K

W

/

R

S

T

R

T

S

T

O

P

A

C

K

W

R

T

R

E

A

D

N

O

A

C

K

M

S

B

L

S

B

SCL

SDA

Figure 27 Reading from a single register