Confidential

Datasheet Version 1.1

Mar. 2015. Revision 1.1

MagnaChip Semiconductor Ltd.

13

SCL

SDA

START

STOP

Figure 22 Timing Diagram on I

DATA VALIDITY

The data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of

the data line can only change when the clock signal on the SCL line is LOW.

SCL

SDA

DATA LINE STABLE

DATA VALID

DATA CHANGE

ALLOWED

Figure 23

Data validity on I

DATA

ACKNOWLEGE

The master (uP) puts a resistive HIGH level on the SDA line during the acknowledge bit. The MSB is

transferred first. One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse. Any change in the SDA line at this time will be interpreted

as a control signal.

1

2

3

4

5

6

7

8

9

MSB

LSB

START

ACKNOWLEDGEMENT

FROM SLAVE

SCL

SDA

Figure 24 Data acknowledge on I

WRITING TO A SINGLE REGISTER

Writing to a single register starts with a START bit followed by the 7 bit device address of MAP7102. The

8th bit is the W/R bit, which is 0 in this case. W/R=1 means a reading operation. Then the master waits for

an acknowledge from MAP7102. Then the 8 bit address of register is sent to MAP7102. It is also followed

by an acknowledge pulse. The last transmitted byte is the data that is going to be written to the register. It is

again followed by an acknowledge pulse from MAP7102. The master then generates a STOP bit and the

communication is over.